`include "cpu.vh"
"""
+import string
from migen import *
from migen.fhdl import verilog
+from migen.fhdl.structure import _Operator
from riscvdefs import *
from cpudefs import *
+class MemoryInterface:
+ fetch_address = Signal(32, name="memory_interface_fetch_address") # XXX [2:]
+ fetch_data = Signal(32, name="memory_interface_fetch_data")
+ fetch_valid = Signal(name="memory_interface_fetch_valid")
+ rw_address= Signal(32, name="memory_interface_rw_address") # XXX [2:]
+ rw_byte_mask = Signal(4, name="memory_interface_rw_byte_mask")
+ rw_read_not_write = Signal(name="memory_interface_rw_read_not_write")
+ rw_active = Signal(name="memory_interface_rw_active")
+ rw_data_in = Signal(32, name="memory_interface_rw_data_in")
+ rw_data_out = Signal(32, name="memory_interface_rw_data_out")
+ rw_address_valid = Signal(name="memory_interface_rw_address_valid")
+ rw_wait = Signal(name="memory_interface_rw_wait")
+
+
+class Decoder:
+ funct7 = Signal(7, name="decoder_funct7")
+ funct3 = Signal(3, name="decoder_funct3")
+ rd = Signal(5, name="decoder_rd")
+ rs1 = Signal(5, name="decoder_rs1")
+ rs2 = Signal(5, name="decoder_rs2")
+ immediate = Signal(32, name="decoder_immediate")
+ opcode = Signal(7, name="decoder_opcode")
+ act = Signal(decode_action, name="decoder_action")
+
+class MStatus:
+ def __init__(self, comb, sync):
+ self.comb = comb
+ self.sync = sync
+ self.mpie = Signal(name="mstatus_mpie")
+ self.mie = Signal(name="mstatus_mie")
+ self.mprv = Signal(name="mstatus_mprv")
+ self.tsr = Signal(name="mstatus_tsr")
+ self.tw = Signal(name="mstatus_tw")
+ self.tvm = Signal(name="mstatus_tvm")
+ self.mxr = Signal(name="mstatus_mxr")
+ self._sum = Signal(name="mstatus_sum")
+ self.xs = Signal(name="mstatus_xs")
+ self.fs = Signal(name="mstatus_fs")
+ self.mpp = Signal(2, name="mstatus_mpp")
+ self.spp = Signal(name="mstatus_spp")
+ self.spie = Signal(name="mstatus_spie")
+ self.upie = Signal(name="mstatus_upie")
+ self.sie = Signal(name="mstatus_sie")
+ self.uie = Signal(name="mstatus_uie")
+
+ for n in dir(self):
+ if n in ['make', 'mpp', 'comb', 'sync'] or n.startswith("_"):
+ continue
+ self.comb += getattr(self, n).eq(0x0)
+ self.comb += self.mpp.eq(0b11)
+
+ self.sync += self.mie.eq(0)
+ self.sync += self.mpie.eq(0)
+
+ def make(self):
+ return Cat(
+ self.uie, self.sie, Constant(0), self.mie,
+ self.upie, self.spie, Constant(0), self.mpie,
+ self.spp, Constant(0, 2), self.mpp,
+ self.fs, self.xs, self.mprv, self._sum,
+ self.mxr, self.tvm, self.tw, self.tsr,
+ Constant(0, 8),
+ (self.xs == Constant(0b11, 2)) | (self.fs == Constant(0b11, 2))
+ )
+
+
+class MIE:
+ def __init__(self, comb, sync):
+ self.comb = comb
+ self.sync = sync
+ self.meie = Signal(name="mie_meie")
+ self.mtie = Signal(name="mie_mtie")
+ self.msie = Signal(name="mie_msie")
+ self.ueie = Signal(name="mie_ueie")
+ self.stie = Signal(name="mie_stie")
+ self.utie = Signal(name="mie_utie")
+ self.ssie = Signal(name="mie_ssie")
+ self.usie = Signal(name="mie_usie")
+
+ for n in dir(self):
+ if n in ['make', 'comb', 'sync'] or n.startswith("_"):
+ continue
+ self.comb += getattr(self, n).eq(0x0)
+
+ self.sync += self.meie.eq(0)
+ self.sync += self.mtie.eq(0)
+ self.sync += self.msie.eq(0)
+
+class MIP:
+ def __init__(self, comb, sync):
+ self.comb = comb
+ self.sync = sync
+ self.meip = Signal(name="mip_meip") # TODO: implement ext interrupts
+ self.seip = Signal(name="mip_seip")
+ self.ueip = Signal(name="mip_uiep")
+ self.mtip = Signal(name="mip_mtip") # TODO: implement timer interrupts
+ self.stip = Signal(name="mip_stip")
+ self.msip = Signal(name="mip_stip")
+ self.utip = Signal(name="mip_utip")
+ self.ssip = Signal(name="mip_ssip")
+ self.usip = Signal(name="mip_usip")
+
+ for n in dir(self):
+ if n in ['comb', 'sync'] or n.startswith("_"):
+ continue
+ self.comb += getattr(self, n).eq(0x0)
+
+
+class M:
+ def __init__(self, comb, sync):
+ self.comb = comb
+ self.sync = sync
+ self.mcause = Signal(32)
+ self.mepc = Signal(32)
+ self.mscratch = Signal(32)
+ self.sync += self.mcause.eq(0)
+ self.sync += self.mepc.eq(0) # 32'hXXXXXXXX;
+ self.sync += self.mscratch.eq(0) # 32'hXXXXXXXX;
+
+class Misa:
+
+ def __init__(self, comb, sync):
+ self.comb = comb
+ self.sync = sync
+ self.misa = Signal(32)
+ cl = []
+ for l in list(string.ascii_lowercase):
+ value = 1 if l == 'i' else 0
+ cl.append(Constant(value))
+ cl.append(Constant(0, 4))
+ cl.append(Constant(0b01, 2))
+ self.comb += self.misa.eq(Cat(cl))
+
+
class CPU(Module):
- """
"""
+ """
+
+ def get_ls_misaligned(self, ls, funct3, load_store_address_low_2):
+ return Case(funct3[:2],
+ { F3.sb: ls.eq(Constant(0)),
+ F3.sh: ls.eq(load_store_address_low_2[0] != 0),
+ F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)),
+ "default": ls.eq(Constant(1))
+ })
+
+ def get_lsbm(self, dc):
+ return Cat(Constant(1),
+ Mux((dc.funct3[1] | dc.funct3[0]),
+ Constant(1), Constant(0)),
+ Mux((dc.funct3[1]),
+ Constant(0b11, 2), Constant(0, 2)))
+
+ # XXX this happens to get done by various self.sync actions
+ #def reset_to_initial(self, m, mstatus, mie, registers):
+ # return [m.mcause.eq(0),
+ # ]
+
+ def write_register(self, register_number, value):
+ return If(register_number != 0,
+ self.registers[register_number].eq(value)
+ )
+
+ def evaluate_csr_funct3_op(self, funct3, previous_value, written_value):
+ c = { "default": Constant(0, 32)}
+ for f in [F3.csrrw, F3.csrrwi]: c[f] = written_value
+ for f in [F3.csrrs, F3.csrrsi]: c[f] = written_value | previous_value
+ for f in [F3.csrrc, F3.csrrci]: c[f] = ~written_value & previous_value
+ return Case(funct3, c)
def __init__(self):
- #self.clk = ClockSignal()
- #self.reset = ResetSignal()
+ self.clk = ClockSignal()
+ self.reset = ResetSignal()
self.tty_write = Signal()
self.tty_write_data = Signal(8)
self.tty_write_busy = Signal()
l = []
for i in range(31):
- l.append(Signal(32, name="register%d" % i))
+ r = Signal(32, name="register%d" % i)
+ l.append(r)
+ self.sync += r.eq(Constant(0, 32))
self.registers = Array(l)
- #self.sync += self.registers[0].eq(0)
- #self.sync += self.registers[1].eq(0)
-
- memory_interface_fetch_address = Signal(32)[2:]
- memory_interface_fetch_data = Signal(32)
- memory_interface_fetch_valid = Signal()
- memory_interface_rw_address= Signal(32)[2:]
- memory_interface_rw_byte_mask = Signal(4)
- memory_interface_rw_read_not_write = Signal()
- memory_interface_rw_active = Signal()
- memory_interface_rw_data_in = Signal(32)
- memory_interface_rw_data_out = Signal(32)
- memory_interface_rw_address_valid = Signal()
- memory_interface_rw_wait = Signal()
-
- mi = Instance("cpu_memory_interface",
+ mi = MemoryInterface()
+
+ mii = Instance("cpu_memory_interface", name="memory_instance",
p_ram_size = ram_size,
p_ram_start = ram_start,
i_clk=ClockSignal(),
i_rst=ResetSignal(),
- i_fetch_address = memory_interface_fetch_address,
- o_fetch_data = memory_interface_fetch_data,
- o_fetch_valid = memory_interface_fetch_valid,
- i_rw_address = memory_interface_rw_address,
- i_rw_byte_mask = memory_interface_rw_byte_mask,
- i_rw_read_not_write = memory_interface_rw_read_not_write,
- i_rw_active = memory_interface_rw_active,
- i_rw_data_in = memory_interface_rw_data_in,
- o_rw_data_out = memory_interface_rw_data_out,
- o_rw_address_valid = memory_interface_rw_address_valid,
- o_rw_wait = memory_interface_rw_wait,
+ i_fetch_address = mi.fetch_address,
+ o_fetch_data = mi.fetch_data,
+ o_fetch_valid = mi.fetch_valid,
+ i_rw_address = mi.rw_address,
+ i_rw_byte_mask = mi.rw_byte_mask,
+ i_rw_read_not_write = mi.rw_read_not_write,
+ i_rw_active = mi.rw_active,
+ i_rw_data_in = mi.rw_data_in,
+ o_rw_data_out = mi.rw_data_out,
+ o_rw_address_valid = mi.rw_address_valid,
+ o_rw_wait = mi.rw_wait,
o_tty_write = self.tty_write,
o_tty_write_data = self.tty_write_data,
i_tty_write_busy = self.tty_write_busy,
o_led_1 = self.led_1,
o_led_3 = self.led_3
)
- self.specials += mi
-
-"""
- cpu_memory_interface #(
- .ram_size(ram_size),
- .ram_start(ram_start)
- ) memory_interface(
- .clk(clk),
- .reset(reset),
- .fetch_address(memory_interface_fetch_address),
- .fetch_data(memory_interface_fetch_data),
- .fetch_valid(memory_interface_fetch_valid),
- .rw_address(memory_interface_rw_address),
- .rw_byte_mask(memory_interface_rw_byte_mask),
- .rw_read_not_write(memory_interface_rw_read_not_write),
- .rw_active(memory_interface_rw_active),
- .rw_data_in(memory_interface_rw_data_in),
- .rw_data_out(memory_interface_rw_data_out),
- .rw_address_valid(memory_interface_rw_address_valid),
- .rw_wait(memory_interface_rw_wait),
- .tty_write(tty_write),
- .tty_write_data(tty_write_data),
- .tty_write_busy(tty_write_busy),
- .switch_2(switch_2),
- .switch_3(switch_3),
- .led_1(led_1),
- .led_3(led_3)
- );
-"""
+ self.specials += mii
+
+ fetch_act = Signal(fetch_action)
+ fetch_target_pc = Signal(32)
+ fetch_output_pc = Signal(32)
+ fetch_output_instruction = Signal(32)
+ fetch_output_st = Signal(fetch_output_state)
+
+ fs = Instance("CPUFetchStage", name="fetch_stage",
+ i_clk=ClockSignal(),
+ i_rst=ResetSignal(),
+ o_memory_interface_fetch_address = mi.fetch_address,
+ i_memory_interface_fetch_data = mi.fetch_data,
+ i_memory_interface_fetch_valid = mi.fetch_valid,
+ i_fetch_action = fetch_act,
+ i_target_pc = fetch_target_pc,
+ o_output_pc = fetch_output_pc,
+ o_output_instruction = fetch_output_instruction,
+ o_output_state = fetch_output_st,
+ i_reset_vector = reset_vector,
+ i_mtvec = mtvec,
+ )
+ self.specials += fs
+
+ dc = Decoder()
+
+ cd = Instance("CPUDecoder", name="decoder",
+ i_instruction = fetch_output_instruction,
+ o_funct7 = dc.funct7,
+ o_funct3 = dc.funct3,
+ o_rd = dc.rd,
+ o_rs1 = dc.rs1,
+ o_rs2 = dc.rs2,
+ o_immediate = dc.immediate,
+ o_opcode = dc.opcode,
+ o_decode_action = dc.act
+ )
+ self.specials += cd
+
+ register_rs1 = Signal(32)
+ register_rs2 = Signal(32)
+ self.comb += If(dc.rs1 == 0,
+ register_rs1.eq(0)
+ ).Else(
+ register_rs1.eq(self.registers[dc.rs1-1]))
+ self.comb += If(dc.rs2 == 0,
+ register_rs2.eq(0)
+ ).Else(
+ register_rs2.eq(self.registers[dc.rs2-1]))
+
+ load_store_address = Signal(32)
+ load_store_address_low_2 = Signal(2)
+
+ self.comb += load_store_address.eq(dc.immediate + register_rs1)
+ self.comb += load_store_address_low_2.eq(
+ dc.immediate[:2] + register_rs1[:2])
+
+ load_store_misaligned = Signal()
+
+ lsa = self.get_ls_misaligned(load_store_misaligned, dc.funct3,
+ load_store_address_low_2)
+ self.comb += lsa
+
+ # XXX rwaddr not 31:2 any more
+ self.comb += mi.rw_address.eq(load_store_address[2:])
+
+ unshifted_load_store_byte_mask = Signal(4)
+
+ self.comb += unshifted_load_store_byte_mask.eq(self.get_lsbm(dc))
+
+ # XXX yuck. this will cause migen simulation to fail
+ # (however conversion to verilog works)
+ self.comb += mi.rw_byte_mask.eq(
+ _Operator("<<", [unshifted_load_store_byte_mask,
+ load_store_address_low_2]))
+
+ # XXX not obvious
+ b3 = Mux(load_store_address_low_2[1],
+ Mux(load_store_address_low_2[0], register_rs2[0:8],
+ register_rs2[8:16]),
+ Mux(load_store_address_low_2[0], register_rs2[16:24],
+ register_rs2[24:32]))
+ b2 = Mux(load_store_address_low_2[1], register_rs2[0:8],
+ register_rs2[16:24])
+ b1 = Mux(load_store_address_low_2[0], register_rs2[0:8],
+ register_rs2[8:16])
+ b0 = register_rs2[0:8]
+
+ self.comb += mi.rw_data_in.eq(Cat(b0, b1, b2, b3))
+
+ # XXX not obvious
+ unmasked_loaded_value = Signal(32)
+
+ b0 = Mux(load_store_address_low_2[1],
+ Mux(load_store_address_low_2[0], mi.rw_data_out[24:32],
+ mi.rw_data_out[16:24]),
+ Mux(load_store_address_low_2[0], mi.rw_data_out[15:8],
+ mi.rw_data_out[0:8]))
+ b1 = Mux(load_store_address_low_2[1], mi.rw_data_out[24:31],
+ mi.rw_data_out[8:16])
+ b23 = mi.rw_data_out[16:32]
+
+ self.comb += unmasked_loaded_value.eq(Cat(b0, b1, b23))
+
+ # XXX not obvious
+ loaded_value = Signal(32)
+
+ b0 = unmasked_loaded_value[0:8]
+ b1 = Mux(dc.funct3[0:2] == 0,
+ Replicate(~dc.funct3[2] & unmasked_loaded_value[7], 8),
+ unmasked_loaded_value[8:16])
+ b2 = Mux(dc.funct3[1] == 0,
+ Replicate(~dc.funct3[2] &
+ Mux(dc.funct3[0], unmasked_loaded_value[15],
+ unmasked_loaded_value[7]),
+ 16),
+ unmasked_loaded_value[16:32])
+
+ self.comb += loaded_value.eq(Cat(b0, b1, b2))
+
+ self.comb += mi.rw_active.eq(~self.reset
+ & (fetch_output_st == fetch_output_state_valid)
+ & ~load_store_misaligned
+ & ((dc.act & (DA.load | DA.store)) != 0))
+
+ self.comb += mi.rw_read_not_write.eq(~dc.opcode[5])
+
+ # alu
+ alu_a = Signal(32)
+ alu_b = Signal(32)
+ alu_result = Signal(32)
+
+ self.comb += alu_a.eq(register_rs1)
+ self.comb += alu_b.eq(Mux(dc.opcode[5],
+ register_rs2,
+ dc.immediate))
+
+ ali = Instance("cpu_alu", name="alu",
+ i_funct7 = dc.funct7,
+ i_funct3 = dc.funct3,
+ i_opcode = dc.opcode,
+ i_a = alu_a,
+ i_b = alu_b,
+ o_result = alu_result
+ )
+ self.specials += ali
+
+ lui_auipc_result = Signal(32)
+ self.comb += lui_auipc_result.eq(Mux(dc.opcode[5],
+ dc.immediate,
+ dc.immediate + fetch_output_pc))
+
+ self.comb += fetch_target_pc.eq(Cat(0,
+ Mux(dc.opcode != OP.jalr,
+ fetch_output_pc[1:32],
+ register_rs1[1:32] + dc.immediate[1:32])))
+
+ misaligned_jump_target = Signal()
+ self.comb += misaligned_jump_target.eq(fetch_target_pc[1])
+
+ branch_arg_a = Signal(32)
+ branch_arg_b = Signal(32)
+ self.comb += branch_arg_a.eq(Cat( register_rs1[0:31],
+ register_rs1[31] ^ ~dc.funct3[1]))
+ self.comb += branch_arg_b.eq(Cat( register_rs2[0:31],
+ register_rs2[31] ^ ~dc.funct3[1]))
+
+ branch_taken = Signal()
+ self.comb += branch_taken.eq(dc.funct3[0] ^
+ Mux(dc.funct3[2],
+ branch_arg_a < branch_arg_b,
+ branch_arg_a == branch_arg_b))
+
+ m = M(self.comb, self.sync)
+ mstatus = MStatus(self.comb, self.sync)
+ mie = MIE(self.comb, self.sync)
+
+ misa = Misa(self.comb, self.sync)
+
+ mvendorid = Signal(32)
+ marchid = Signal(32)
+ mimpid = Signal(32)
+ mhartid = Signal(32)
+ self.comb += mvendorid.eq(Constant(0, 32))
+ self.comb += marchid.eq(Constant(0, 32))
+ self.comb += mimpid.eq(Constant(0, 32))
+ self.comb += mhartid.eq(Constant(0, 32))
+
+ mip = MIP(self.comb, self.sync)
+
+ csr_op_is_valid = Signal()
if __name__ == "__main__":
example = CPU()
}))
"""
-module cpu(
- input clk,
- input reset,
- output tty_write,
- output [7:0] tty_write_data,
- input tty_write_busy,
- input switch_2,
- input switch_3,
- output led_1,
- output led_3
- );
-
- parameter ram_size = 'h8000;
- parameter ram_start = 32'h1_0000;
- parameter reset_vector = ram_start;
- parameter mtvec = ram_start + 'h40;
-
- reg [31:0] registers[31:1];
-
- wire [31:2] memory_interface_fetch_address;
- wire [31:0] memory_interface_fetch_data;
- wire memory_interface_fetch_valid;
- wire [31:2] memory_interface_rw_address;
- wire [3:0] memory_interface_rw_byte_mask;
- wire memory_interface_rw_read_not_write;
- wire memory_interface_rw_active;
- wire [31:0] memory_interface_rw_data_in;
- wire [31:0] memory_interface_rw_data_out;
- wire memory_interface_rw_address_valid;
- wire memory_interface_rw_wait;
-
- cpu_memory_interface #(
- .ram_size(ram_size),
- .ram_start(ram_start)
- ) memory_interface(
- .clk(clk),
- .reset(reset),
- .fetch_address(memory_interface_fetch_address),
- .fetch_data(memory_interface_fetch_data),
- .fetch_valid(memory_interface_fetch_valid),
- .rw_address(memory_interface_rw_address),
- .rw_byte_mask(memory_interface_rw_byte_mask),
- .rw_read_not_write(memory_interface_rw_read_not_write),
- .rw_active(memory_interface_rw_active),
- .rw_data_in(memory_interface_rw_data_in),
- .rw_data_out(memory_interface_rw_data_out),
- .rw_address_valid(memory_interface_rw_address_valid),
- .rw_wait(memory_interface_rw_wait),
- .tty_write(tty_write),
- .tty_write_data(tty_write_data),
- .tty_write_busy(tty_write_busy),
- .switch_2(switch_2),
- .switch_3(switch_3),
- .led_1(led_1),
- .led_3(led_3)
- );
-
- wire `fetch_action fetch_action;
- wire [31:0] fetch_target_pc;
- wire [31:0] fetch_output_pc;
- wire [31:0] fetch_output_instruction;
- wire `fetch_output_state fetch_output_state;
-
- cpu_fetch_stage #(
- .reset_vector(reset_vector),
- .mtvec(mtvec)
- ) fetch_stage(
- .clk(clk),
- .reset(reset),
- .memory_interface_fetch_address(memory_interface_fetch_address),
- .memory_interface_fetch_data(memory_interface_fetch_data),
- .memory_interface_fetch_valid(memory_interface_fetch_valid),
- .fetch_action(fetch_action),
- .target_pc(fetch_target_pc),
- .output_pc(fetch_output_pc),
- .output_instruction(fetch_output_instruction),
- .output_state(fetch_output_state)
- );
-
- wire [6:0] decoder_funct7;
- wire [2:0] decoder_funct3;
- wire [4:0] decoder_rd;
- wire [4:0] decoder_rs1;
- wire [4:0] decoder_rs2;
- wire [31:0] decoder_immediate;
- wire [6:0] decoder_opcode;
- wire `decode_action decode_action;
-
- cpu_decoder decoder(
- .instruction(fetch_output_instruction),
- .funct7(decoder_funct7),
- .funct3(decoder_funct3),
- .rd(decoder_rd),
- .rs1(decoder_rs1),
- .rs2(decoder_rs2),
- .immediate(decoder_immediate),
- .opcode(decoder_opcode),
- .decode_action(decode_action));
-
- wire [31:0] register_rs1 = (decoder_rs1 == 0) ? 0 : registers[decoder_rs1];
- wire [31:0] register_rs2 = (decoder_rs2 == 0) ? 0 : registers[decoder_rs2];
-
- wire [31:0] load_store_address = decoder_immediate + register_rs1;
-
- wire [1:0] load_store_address_low_2 = decoder_immediate[1:0] + register_rs1[1:0];
-
- function get_load_store_misaligned(
- input [2:0] funct3,
- input [1:0] load_store_address_low_2
- );
- begin
- case(funct3[1:0])
- `funct3_sb:
- get_load_store_misaligned = 0;
- `funct3_sh:
- get_load_store_misaligned = load_store_address_low_2[0] != 0;
- `funct3_sw:
- get_load_store_misaligned = load_store_address_low_2[1:0] != 0;
- default:
- get_load_store_misaligned = 1'bX;
- endcase
- end
- endfunction
-
- wire load_store_misaligned = get_load_store_misaligned(decoder_funct3, load_store_address_low_2);
-
- assign memory_interface_rw_address = load_store_address[31:2];
-
- wire [3:0] unshifted_load_store_byte_mask = {decoder_funct3[1] ? 2'b11 : 2'b00, (decoder_funct3[1] | decoder_funct3[0]) ? 1'b1 : 1'b0, 1'b1};
-
- assign memory_interface_rw_byte_mask = unshifted_load_store_byte_mask << load_store_address_low_2;
-
- assign memory_interface_rw_data_in[31:24] = load_store_address_low_2[1]
- ? (load_store_address_low_2[0] ? register_rs2[7:0] : register_rs2[15:8])
- : (load_store_address_low_2[0] ? register_rs2[23:16] : register_rs2[31:24]);
- assign memory_interface_rw_data_in[23:16] = load_store_address_low_2[1] ? register_rs2[7:0] : register_rs2[23:16];
- assign memory_interface_rw_data_in[15:8] = load_store_address_low_2[0] ? register_rs2[7:0] : register_rs2[15:8];
- assign memory_interface_rw_data_in[7:0] = register_rs2[7:0];
-
- wire [31:0] unmasked_loaded_value;
-
- assign unmasked_loaded_value[7:0] = load_store_address_low_2[1]
- ? (load_store_address_low_2[0] ? memory_interface_rw_data_out[31:24] : memory_interface_rw_data_out[23:16])
- : (load_store_address_low_2[0] ? memory_interface_rw_data_out[15:8] : memory_interface_rw_data_out[7:0]);
- assign unmasked_loaded_value[15:8] = load_store_address_low_2[1] ? memory_interface_rw_data_out[31:24] : memory_interface_rw_data_out[15:8];
- assign unmasked_loaded_value[31:16] = memory_interface_rw_data_out[31:16];
-
- wire [31:0] loaded_value;
-
- assign loaded_value[7:0] = unmasked_loaded_value[7:0];
- assign loaded_value[15:8] = decoder_funct3[1:0] == 0 ? ({8{~decoder_funct3[2] & unmasked_loaded_value[7]}}) : unmasked_loaded_value[15:8];
- assign loaded_value[31:16] = decoder_funct3[1] == 0 ? ({16{~decoder_funct3[2] & (decoder_funct3[0] ? unmasked_loaded_value[15] : unmasked_loaded_value[7])}}) : unmasked_loaded_value[31:16];
-
- assign memory_interface_rw_active = ~reset
- & (fetch_output_state == `fetch_output_state_valid)
- & ~load_store_misaligned
- & ((decode_action & (`decode_action_load | `decode_action_store)) != 0);
-
- assign memory_interface_rw_read_not_write = ~decoder_opcode[5];
-
- wire [31:0] alu_a = register_rs1;
- wire [31:0] alu_b = decoder_opcode[5] ? register_rs2 : decoder_immediate;
- wire [31:0] alu_result;
-
- cpu_alu alu(
- .funct7(decoder_funct7),
- .funct3(decoder_funct3),
- .opcode(decoder_opcode),
- .a(alu_a),
- .b(alu_b),
- .result(alu_result)
- );
-
- wire [31:0] lui_auipc_result = decoder_opcode[5] ? decoder_immediate : decoder_immediate + fetch_output_pc;
-
- assign fetch_target_pc[31:1] = ((decoder_opcode != `opcode_jalr ? fetch_output_pc[31:1] : register_rs1[31:1]) + decoder_immediate[31:1]);
- assign fetch_target_pc[0] = 0;
-
- wire misaligned_jump_target = fetch_target_pc[1];
-
- wire [31:0] branch_arg_a = {register_rs1[31] ^ ~decoder_funct3[1], register_rs1[30:0]};
- wire [31:0] branch_arg_b = {register_rs2[31] ^ ~decoder_funct3[1], register_rs2[30:0]};
-
- wire branch_taken = decoder_funct3[0] ^ (decoder_funct3[2] ? branch_arg_a < branch_arg_b : branch_arg_a == branch_arg_b);
-
- reg [31:0] mcause = 0;
- reg [31:0] mepc = 32'hXXXXXXXX;
- reg [31:0] mscratch = 32'hXXXXXXXX;
-
- reg mstatus_mpie = 1'bX;
- reg mstatus_mie = 0;
- parameter mstatus_mprv = 0;
- parameter mstatus_tsr = 0;
- parameter mstatus_tw = 0;
- parameter mstatus_tvm = 0;
- parameter mstatus_mxr = 0;
- parameter mstatus_sum = 0;
- parameter mstatus_xs = 0;
- parameter mstatus_fs = 0;
- parameter mstatus_mpp = 2'b11;
- parameter mstatus_spp = 0;
- parameter mstatus_spie = 0;
- parameter mstatus_upie = 0;
- parameter mstatus_sie = 0;
- parameter mstatus_uie = 0;
-
- reg mie_meie = 1'bX;
- reg mie_mtie = 1'bX;
- reg mie_msie = 1'bX;
- parameter mie_seie = 0;
- parameter mie_ueie = 0;
- parameter mie_stie = 0;
- parameter mie_utie = 0;
- parameter mie_ssie = 0;
- parameter mie_usie = 0;
-
- task reset_to_initial;
- begin
- mcause = 0;
- mepc = 32'hXXXXXXXX;
- mscratch = 32'hXXXXXXXX;
- mstatus_mie = 0;
- mstatus_mpie = 1'bX;
- mie_meie = 1'bX;
- mie_mtie = 1'bX;
- mie_msie = 1'bX;
- registers['h01] <= 32'hXXXXXXXX;
- registers['h02] <= 32'hXXXXXXXX;
- registers['h03] <= 32'hXXXXXXXX;
- registers['h04] <= 32'hXXXXXXXX;
- registers['h05] <= 32'hXXXXXXXX;
- registers['h06] <= 32'hXXXXXXXX;
- registers['h07] <= 32'hXXXXXXXX;
- registers['h08] <= 32'hXXXXXXXX;
- registers['h09] <= 32'hXXXXXXXX;
- registers['h0A] <= 32'hXXXXXXXX;
- registers['h0B] <= 32'hXXXXXXXX;
- registers['h0C] <= 32'hXXXXXXXX;
- registers['h0D] <= 32'hXXXXXXXX;
- registers['h0E] <= 32'hXXXXXXXX;
- registers['h0F] <= 32'hXXXXXXXX;
- registers['h10] <= 32'hXXXXXXXX;
- registers['h11] <= 32'hXXXXXXXX;
- registers['h12] <= 32'hXXXXXXXX;
- registers['h13] <= 32'hXXXXXXXX;
- registers['h14] <= 32'hXXXXXXXX;
- registers['h15] <= 32'hXXXXXXXX;
- registers['h16] <= 32'hXXXXXXXX;
- registers['h17] <= 32'hXXXXXXXX;
- registers['h18] <= 32'hXXXXXXXX;
- registers['h19] <= 32'hXXXXXXXX;
- registers['h1A] <= 32'hXXXXXXXX;
- registers['h1B] <= 32'hXXXXXXXX;
- registers['h1C] <= 32'hXXXXXXXX;
- registers['h1D] <= 32'hXXXXXXXX;
- registers['h1E] <= 32'hXXXXXXXX;
- registers['h1F] <= 32'hXXXXXXXX;
- end
- endtask
-
- task write_register(input [4:0] register_number, input [31:0] value);
- begin
- if(register_number != 0)
- registers[register_number] <= value;
- end
- endtask
-
- function [31:0] evaluate_csr_funct3_operation(input [2:0] funct3, input [31:0] previous_value, input [31:0] written_value);
- begin
- case(funct3)
- `funct3_csrrw, `funct3_csrrwi:
- evaluate_csr_funct3_operation = written_value;
- `funct3_csrrs, `funct3_csrrsi:
- evaluate_csr_funct3_operation = written_value | previous_value;
- `funct3_csrrc, `funct3_csrrci:
- evaluate_csr_funct3_operation = ~written_value & previous_value;
- default:
- evaluate_csr_funct3_operation = 32'hXXXXXXXX;
- endcase
- end
- endfunction
-
- parameter misa_a = 1'b0;
- parameter misa_b = 1'b0;
- parameter misa_c = 1'b0;
- parameter misa_d = 1'b0;
- parameter misa_e = 1'b0;
- parameter misa_f = 1'b0;
- parameter misa_g = 1'b0;
- parameter misa_h = 1'b0;
- parameter misa_i = 1'b1;
- parameter misa_j = 1'b0;
- parameter misa_k = 1'b0;
- parameter misa_l = 1'b0;
- parameter misa_m = 1'b0;
- parameter misa_n = 1'b0;
- parameter misa_o = 1'b0;
- parameter misa_p = 1'b0;
- parameter misa_q = 1'b0;
- parameter misa_r = 1'b0;
- parameter misa_s = 1'b0;
- parameter misa_t = 1'b0;
- parameter misa_u = 1'b0;
- parameter misa_v = 1'b0;
- parameter misa_w = 1'b0;
- parameter misa_x = 1'b0;
- parameter misa_y = 1'b0;
- parameter misa_z = 1'b0;
- parameter misa = {
- 2'b01,
- 4'b0,
- misa_z,
- misa_y,
- misa_x,
- misa_w,
- misa_v,
- misa_u,
- misa_t,
- misa_s,
- misa_r,
- misa_q,
- misa_p,
- misa_o,
- misa_n,
- misa_m,
- misa_l,
- misa_k,
- misa_j,
- misa_i,
- misa_h,
- misa_g,
- misa_f,
- misa_e,
- misa_d,
- misa_c,
- misa_b,
- misa_a};
-
- parameter mvendorid = 32'b0;
- parameter marchid = 32'b0;
- parameter mimpid = 32'b0;
- parameter mhartid = 32'b0;
-
- function [31:0] make_mstatus(input mstatus_tsr,
- input mstatus_tw,
- input mstatus_tvm,
- input mstatus_mxr,
- input mstatus_sum,
- input mstatus_mprv,
- input [1:0] mstatus_xs,
- input [1:0] mstatus_fs,
- input [1:0] mstatus_mpp,
- input mstatus_spp,
- input mstatus_mpie,
- input mstatus_spie,
- input mstatus_upie,
- input mstatus_mie,
- input mstatus_sie,
- input mstatus_uie);
- begin
- make_mstatus = {(mstatus_xs == 2'b11) | (mstatus_fs == 2'b11),
- 8'b0,
- mstatus_tsr,
- mstatus_tw,
- mstatus_tvm,
- mstatus_mxr,
- mstatus_sum,
- mstatus_mprv,
- mstatus_xs,
- mstatus_fs,
- mstatus_mpp,
- 2'b0,
- mstatus_spp,
- mstatus_mpie,
- 1'b0,
- mstatus_spie,
- mstatus_upie,
- mstatus_mie,
- 1'b0,
- mstatus_sie,
- mstatus_uie};
- end
- endfunction
-
- wire mip_meip = 0; // TODO: implement external interrupts
- parameter mip_seip = 0;
- parameter mip_ueip = 0;
- wire mip_mtip = 0; // TODO: implement timer interrupts
- parameter mip_stip = 0;
- parameter mip_utip = 0;
- parameter mip_msip = 0;
- parameter mip_ssip = 0;
- parameter mip_usip = 0;
-
- wire csr_op_is_valid;
function `fetch_action get_fetch_action(
input `fetch_output_state fetch_output_state,
endcase
end
endfunction
-
+
assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes);
wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
projects / rv32.git / blobdiff