sifive-blocks.git
21 months agospi: SPIParamsBase param needs to be public master
Henry Cook [Sun, 4 Mar 2018 21:26:19 +0000 (13:26 -0800)]
spi: SPIParamsBase param needs to be public

21 months agoRemove cloneTypes in favor of autoclonetype (#51)
Jack Koenig [Sun, 4 Mar 2018 18:29:51 +0000 (10:29 -0800)]
Remove cloneTypes in favor of autoclonetype (#51)

* Remove cloneTypes in favor of autoclonetype

* Consistently use private val for autoclonetype

21 months agoperiphery: bus api update (#50)
Henry Cook [Thu, 1 Mar 2018 09:15:02 +0000 (01:15 -0800)]
periphery: bus api update (#50)

21 months agoBug fix: arbLost should be asserted when bitState =/= s_bit_idle (#49)
solomatnikov [Fri, 23 Feb 2018 20:09:18 +0000 (12:09 -0800)]
Bug fix: arbLost should be asserted when bitState =/= s_bit_idle (#49)

21 months agoMerge pull request #48 from sifive/i2c_int
solomatnikov [Fri, 23 Feb 2018 02:48:09 +0000 (18:48 -0800)]
Merge pull request #48 from sifive/i2c_int

i2c interrupt: allow irq to be cleared

21 months agoDo not allow status read if status.transferInProgress is going to change next cycle i2c_int
Alex Solomatnikov [Fri, 23 Feb 2018 02:43:39 +0000 (18:43 -0800)]
Do not allow status read if status.transferInProgress is going to change next cycle

21 months agoi2c: Allow irq to be cleared
Megan Wachs [Fri, 16 Feb 2018 23:49:09 +0000 (15:49 -0800)]
i2c: Allow irq to be cleared

23 months agouart: Eliminate systemic baud rate error with low divisor values
Albert Ou [Fri, 5 Jan 2018 03:51:24 +0000 (19:51 -0800)]
uart: Eliminate systemic baud rate error with low divisor values

This refactors the receiver logic to compensate for the case of the baud
rate divisor not being multiple of the oversampling period.

Previously, the bit time was effectively rounded to (s * floor(div / s))
cycles, where "s" is the oversampling factor - the number of
intermediate samples for each data bit.  The remainder r = (div % s) was
ignored, thereby resulting in gradually accumulated drift that became
significant for divisor values on the same order of magnitude as "s".

The revised approach inserts the required additional delay by extending
the last "r" samples of a given data bit by one cycle each.

2 years agoMerge pull request #46 from sifive/gpio_iof_pueds
Megan Wachs [Thu, 9 Nov 2017 01:18:02 +0000 (17:18 -0800)]
Merge pull request #46 from sifive/gpio_iof_pueds

GPIO: IOF should not override PUE and DS

2 years agoGPIO: IOF should not override PUE and DS gpio_iof_pueds
Megan Wachs [Wed, 8 Nov 2017 23:15:32 +0000 (15:15 -0800)]
GPIO: IOF should not override PUE and DS

2 years agoPMU: adapt to new chisel API (#45)
Wesley W. Terpstra [Thu, 2 Nov 2017 22:44:02 +0000 (15:44 -0700)]
PMU: adapt to new chisel API (#45)

2 years agodevices: switch to using node-style API (#44)
Wesley W. Terpstra [Sat, 28 Oct 2017 19:29:31 +0000 (12:29 -0700)]
devices: switch to using node-style API (#44)

2 years agosifive-blocks: update to new rocket API (#43)
Wesley W. Terpstra [Thu, 26 Oct 2017 23:10:18 +0000 (16:10 -0700)]
sifive-blocks: update to new rocket API (#43)

2 years agoMerge pull request #42 from sifive/enhanced_to_base_pin
Megan Wachs [Wed, 11 Oct 2017 13:43:41 +0000 (06:43 -0700)]
Merge pull request #42 from sifive/enhanced_to_base_pin

pinctrl: Add the ability to convert EnhancedPin to BasePin

2 years agopinctrl: Add the ability to convert EnhancedPin to BasePin enhanced_to_base_pin
Megan Wachs [Fri, 6 Oct 2017 20:43:23 +0000 (13:43 -0700)]
pinctrl: Add the ability to convert EnhancedPin to BasePin

2 years agoMerge pull request #41 from sifive/pwm_invert
Megan Wachs [Thu, 5 Oct 2017 23:32:26 +0000 (16:32 -0700)]
Merge pull request #41 from sifive/pwm_invert

PWM: Add the ability to invert the output directly in PWM

2 years agoPWM: Add the ability to invert the output directly in PWM (without GPIO pinmux) pwm_invert
Megan Wachs [Mon, 2 Oct 2017 18:13:33 +0000 (11:13 -0700)]
PWM: Add the ability to invert the output directly in PWM (without GPIO pinmux)

2 years agodiplomacy: update to new API (#40)
Wesley W. Terpstra [Wed, 27 Sep 2017 23:33:18 +0000 (16:33 -0700)]
diplomacy: update to new API (#40)

2 years agoMerge pull request #39 from sifive/signal_bundles
Megan Wachs [Mon, 25 Sep 2017 18:21:08 +0000 (11:21 -0700)]
Merge pull request #39 from sifive/signal_bundles

Create Signal Bundles vs just Pins

2 years agoGPIO Pins needs clone type. signal_bundles
Megan Wachs [Fri, 22 Sep 2017 23:38:37 +0000 (16:38 -0700)]
GPIO Pins needs clone type.

2 years agosignal_bundles: add missing file
Megan Wachs [Fri, 22 Sep 2017 20:55:55 +0000 (13:55 -0700)]
signal_bundles: add missing file

2 years agopinctrl: Create extendable Signal classes
Megan Wachs [Fri, 22 Sep 2017 20:17:31 +0000 (13:17 -0700)]
pinctrl: Create extendable Signal classes

2 years agodevice pins: Create classes that can be something other than a Pin subclass
Megan Wachs [Wed, 20 Sep 2017 23:43:42 +0000 (16:43 -0700)]
device pins: Create classes that can be something other than a Pin subclass

2 years agoSPI: Make it easier to build arbitrary bundles
Megan Wachs [Wed, 20 Sep 2017 23:21:21 +0000 (16:21 -0700)]
SPI: Make it easier to build arbitrary bundles

2 years agouart: use PeripheryBusKey (#38)
Henry Cook [Fri, 15 Sep 2017 21:54:10 +0000 (14:54 -0700)]
uart: use PeripheryBusKey (#38)

2 years agoMerge pull request #37 from sifive/synchronizers
Megan Wachs [Thu, 7 Sep 2017 20:34:14 +0000 (13:34 -0700)]
Merge pull request #37 from sifive/synchronizers

remove duplicate ResetCatchAndSync definition

2 years agoshiftregs: Use SyncResetSynchronizerShiftReg primitives where appropriate synchronizers
Megan Wachs [Wed, 6 Sep 2017 17:59:07 +0000 (10:59 -0700)]
shiftregs: Use SyncResetSynchronizerShiftReg primitives where appropriate

2 years agoi2c/uart: Name the synchronizers
Megan Wachs [Wed, 6 Sep 2017 01:40:22 +0000 (18:40 -0700)]
i2c/uart: Name the synchronizers

2 years agogpio: Use Synchronizer for the inputs
Megan Wachs [Wed, 6 Sep 2017 01:35:09 +0000 (18:35 -0700)]
gpio: Use Synchronizer for the inputs

2 years agoi2c, uart: Use Synchronizer primitives for the inputs
Megan Wachs [Wed, 6 Sep 2017 01:32:37 +0000 (18:32 -0700)]
i2c, uart: Use Synchronizer primitives for the inputs

2 years agoShiftRegInit: use the rocket-chip version since it is there now
Megan Wachs [Wed, 6 Sep 2017 00:51:40 +0000 (17:51 -0700)]
ShiftRegInit: use the rocket-chip version since it is there now

2 years agoregs: remove duplicate ShiftReg file which is now in rocket-chip
Megan Wachs [Wed, 6 Sep 2017 00:33:32 +0000 (17:33 -0700)]
regs: remove duplicate ShiftReg file which is now in rocket-chip

2 years agoremove duplicate ResetCatchAndSync definition
Megan Wachs [Fri, 25 Aug 2017 01:12:36 +0000 (18:12 -0700)]
remove duplicate ResetCatchAndSync definition

2 years agoMerge pull request #35 from sifive/spi-buffers
Megan Wachs [Sun, 20 Aug 2017 23:47:01 +0000 (16:47 -0700)]
Merge pull request #35 from sifive/spi-buffers

spi: put a request buffer infront of SPI

2 years agospi: Make memory mapped interface depth a parameter
Megan Wachs [Sun, 20 Aug 2017 19:39:38 +0000 (12:39 -0700)]
spi: Make memory mapped interface depth a parameter

2 years agospi: put a request buffer infront of SPI
Wesley W. Terpstra [Sat, 19 Aug 2017 19:36:28 +0000 (12:36 -0700)]
spi: put a request buffer infront of SPI

This will prevent SPI from blocking other pbus requests.

2 years agoMerge pull request #34 from ss2783/master
Shreesha Srinath [Fri, 18 Aug 2017 21:27:57 +0000 (14:27 -0700)]
Merge pull request #34 from ss2783/master

Updates to go with the fpga-shells directory

2 years agoRenamed ShiftReg to ShiftRegister
Shreesha Srinath [Fri, 18 Aug 2017 01:22:51 +0000 (18:22 -0700)]
Renamed ShiftReg to ShiftRegister

2 years agoUpdates to go with the fpga-shells directory
Shreesha Srinath [Fri, 18 Aug 2017 01:11:07 +0000 (18:11 -0700)]
Updates to go with the fpga-shells directory

2 years agouart: make it easy to simulate large text printouts (#33)
Wesley W. Terpstra [Thu, 10 Aug 2017 23:32:48 +0000 (16:32 -0700)]
uart: make it easy to simulate large text printouts (#33)

2 years agoMerge pull request #31 from ss2783/fix-mockaon
Shreesha Srinath [Fri, 4 Aug 2017 18:46:06 +0000 (11:46 -0700)]
Merge pull request #31 from ss2783/fix-mockaon

mockaon: Adds logic to detect external rtc toggles

2 years agomockaon: Adds logic to detect external rtc toggles
Shreesha Srinath [Thu, 3 Aug 2017 01:11:05 +0000 (18:11 -0700)]
mockaon: Adds logic to detect external rtc toggles

2 years agoMerge pull request #30 from sifive/spi
Albert Ou [Wed, 2 Aug 2017 22:33:11 +0000 (13:33 -0900)]
Merge pull request #30 from sifive/spi

spi: Fix invalid D channel response when flash interface is disabled

2 years agospi: Fix invalid D channel response when flash interface is disabled
Albert Ou [Wed, 2 Aug 2017 20:50:00 +0000 (13:50 -0700)]
spi: Fix invalid D channel response when flash interface is disabled

Issue: When the memory-mapped flash region is accessed while the flash
read mode is disabled (fctrl.en flag is clear), the SPI flash controller
generates an invalid response on the D channel.
This may cause the TileLink bus to deadlock.

Workaround: Software should avoid accessing the memory-mapped flash
region when the SPI controller is not in the flash read mode.

2 years agoallow bundle content params to be specified via a def (#29)
Henry Cook [Wed, 2 Aug 2017 18:46:27 +0000 (11:46 -0700)]
allow bundle content params to be specified via a def (#29)

2 years agospi: remove removed sink arg
Wesley W. Terpstra [Wed, 26 Jul 2017 23:02:44 +0000 (16:02 -0700)]
spi: remove removed sink arg

2 years agoMerge pull request #27 from sifive/typed_pad_ctrl
Yunsup Lee [Tue, 25 Jul 2017 23:37:46 +0000 (16:37 -0700)]
Merge pull request #27 from sifive/typed_pad_ctrl

Seperate GPIO Peripheral Functionality

2 years agomockaon: rename pads to pins
Yunsup Lee [Tue, 25 Jul 2017 22:02:22 +0000 (15:02 -0700)]
mockaon: rename pads to pins

2 years agoPorts: Rename the 'fromXYZPort' to 'fromPort' since it's redundant
Megan Wachs [Tue, 25 Jul 2017 15:36:28 +0000 (08:36 -0700)]
Ports: Rename the 'fromXYZPort' to 'fromPort' since it's redundant

2 years agoMerge remote-tracking branch 'origin/master' into typed_pad_ctrl
Megan Wachs [Tue, 25 Jul 2017 14:05:22 +0000 (07:05 -0700)]
Merge remote-tracking branch 'origin/master' into typed_pad_ctrl

2 years agouart: use PeripheryBusParams.frequency to calculate default divisor (#28)
Yunsup Lee [Tue, 25 Jul 2017 07:56:22 +0000 (00:56 -0700)]
uart: use PeripheryBusParams.frequency to calculate default divisor (#28)

2 years agoMerge remote-tracking branch 'origin/master' into typed_pad_ctrl
Megan Wachs [Mon, 24 Jul 2017 16:17:53 +0000 (09:17 -0700)]
Merge remote-tracking branch 'origin/master' into typed_pad_ctrl

2 years agoperiphery: peripherals now in coreplex (#26)
Henry Cook [Sun, 23 Jul 2017 15:31:44 +0000 (08:31 -0700)]
periphery: peripherals now in coreplex (#26)

* periphery: peripherals now in coreplex

* use fromAsyncFIFOMaster

2 years agogpio: Add missing file
Megan Wachs [Thu, 20 Jul 2017 21:53:34 +0000 (14:53 -0700)]
gpio: Add missing file

2 years agoAdd missing cloneType methods to pin bundles
Megan Wachs [Thu, 20 Jul 2017 18:36:31 +0000 (11:36 -0700)]
Add missing cloneType methods to pin bundles

2 years agoi2c: Remove pluralization on the bundle name, i2c not i2cs
Megan Wachs [Thu, 20 Jul 2017 17:53:44 +0000 (10:53 -0700)]
i2c: Remove pluralization on the bundle name, i2c not i2cs

2 years agoRemove pluralization on interface names. Require clocks and resets explicitly when...
Megan Wachs [Wed, 19 Jul 2017 21:51:50 +0000 (14:51 -0700)]
Remove pluralization on interface names. Require clocks and resets explicitly when necessary

2 years agoMake it possible to adjust the type of pad controls used,
Megan Wachs [Tue, 18 Jul 2017 17:58:04 +0000 (10:58 -0700)]
Make it possible to adjust the type of pad controls used,
and seperate out some of the "GPIO Peripheral" from "Pin Control"

2 years agoRefactor package hierarchy. (#25)
Henry Cook [Fri, 7 Jul 2017 17:48:57 +0000 (10:48 -0700)]
Refactor package hierarchy. (#25)

2 years agovc707 axi enhancements (#24)
Wesley W. Terpstra [Fri, 30 Jun 2017 19:36:33 +0000 (12:36 -0700)]
vc707 axi enhancements (#24)

1 - Print AXI-ID mappings
2 - Use half as many Deinterleaver buffers for the L2 backside
3 - Limit the Q depth on the PCIe control port to 2 (was 1584!)

2 years agomig: fix MemoryDevice to use 'reg' properly
Wesley W. Terpstra [Thu, 29 Jun 2017 20:41:30 +0000 (13:41 -0700)]
mig: fix MemoryDevice to use 'reg' properly

2 years agospi: include mem region (#23)
Wesley W. Terpstra [Thu, 29 Jun 2017 00:46:45 +0000 (17:46 -0700)]
spi: include mem region (#23)

2 years agodiplomacy: add reg-names to devices (#22)
Wesley W. Terpstra [Thu, 29 Jun 2017 00:45:18 +0000 (17:45 -0700)]
diplomacy: add reg-names to devices (#22)

2 years agogpio: Make IOF optional (#21)
Megan Wachs [Mon, 19 Jun 2017 19:41:38 +0000 (12:41 -0700)]
gpio: Make IOF optional (#21)

* gpio: Make IOF optional

* IOF: Make the default false

2 years agomake some base bundle classes easier to clone (#20)
Henry Cook [Thu, 15 Jun 2017 02:47:56 +0000 (19:47 -0700)]
make some base bundle classes easier to clone (#20)

2 years agospi: add dts ranges field for memory mapped spi (#19)
Wesley W. Terpstra [Thu, 15 Jun 2017 00:06:55 +0000 (17:06 -0700)]
spi: add dts ranges field for memory mapped spi (#19)

2 years agoMerge pull request #18 from sifive/lazy-raw-module-imp
Henry Cook [Tue, 13 Jun 2017 22:52:11 +0000 (15:52 -0700)]
Merge pull request #18 from sifive/lazy-raw-module-imp

periphery: convert bundle traits

2 years agoMore Peripheral-to-pins cleanups
Megan Wachs [Tue, 13 Jun 2017 18:00:29 +0000 (11:00 -0700)]
More Peripheral-to-pins cleanups

2 years agoUART: actually return the pins, not just the module. We should do this for the other...
Megan Wachs [Tue, 13 Jun 2017 01:08:35 +0000 (18:08 -0700)]
UART: actually return the pins, not just the module. We should do this for the other peripherals as well

2 years agoGPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they...
Megan Wachs [Tue, 13 Jun 2017 00:53:51 +0000 (17:53 -0700)]
GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful.

2 years agoGPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they...
Megan Wachs [Tue, 13 Jun 2017 00:53:08 +0000 (17:53 -0700)]
GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful.

2 years agoperiphery: convert periphery bundle traits to work with system-level multi-io module
Henry Cook [Mon, 5 Jun 2017 21:33:53 +0000 (14:33 -0700)]
periphery: convert periphery bundle traits to work with system-level multi-io module

2 years agoMerge pull request #17 from sifive/peripheral_options
Megan Wachs [Sat, 10 Jun 2017 05:07:43 +0000 (22:07 -0700)]
Merge pull request #17 from sifive/peripheral_options

Make more peripherals "listable" to allow for 0 or more

2 years agoperipheral_options: Actually compiles
Megan Wachs [Fri, 9 Jun 2017 20:53:22 +0000 (13:53 -0700)]
peripheral_options: Actually compiles

2 years agoSPIFlash: make it listable
Megan Wachs [Thu, 8 Jun 2017 23:29:01 +0000 (16:29 -0700)]
SPIFlash: make it listable

2 years agoGPIO: Make GPIO peripheral another listable one
Megan Wachs [Thu, 8 Jun 2017 23:25:20 +0000 (16:25 -0700)]
GPIO: Make GPIO peripheral another listable one

2 years agovc707axi: track rocketchip API changes (#16)
Wesley W. Terpstra [Fri, 2 Jun 2017 22:56:18 +0000 (15:56 -0700)]
vc707axi: track rocketchip API changes (#16)

2 years agouart: power-on with the right divider for the design (#15)
Wesley W. Terpstra [Sun, 14 May 2017 06:38:20 +0000 (23:38 -0700)]
uart: power-on with the right divider for the design (#15)

2 years agoMerge pull request #14 from sifive/async-pcie
Wesley W. Terpstra [Sat, 13 May 2017 06:15:14 +0000 (23:15 -0700)]
Merge pull request #14 from sifive/async-pcie

Async PCIe

2 years agovc707mig: use an external ibuf
Wesley W. Terpstra [Sat, 13 May 2017 06:07:10 +0000 (23:07 -0700)]
vc707mig: use an external ibuf

This makes it possible to also drive a PLL of our own from the crystal.

2 years agoxilinxvc707pciex1: push to a dedicated clock domain
Wesley W. Terpstra [Sat, 13 May 2017 05:59:48 +0000 (22:59 -0700)]
xilinxvc707pciex1: push to a dedicated clock domain

2 years agoxilinx mig: put a buffer infront of the controller (#13)
Wesley W. Terpstra [Thu, 11 May 2017 18:50:07 +0000 (11:50 -0700)]
xilinx mig: put a buffer infront of the controller (#13)

This makes placement of the L2 and DDR controller easier.

2 years agoxilinxvc707pciex1: better wrapper for AXI4-Lite control node (#12)
Wesley W. Terpstra [Mon, 8 May 2017 08:08:37 +0000 (01:08 -0700)]
xilinxvc707pciex1: better wrapper for AXI4-Lite control node (#12)

2 years agoMerge pull request #10 from sifive/axi-mmio
Henry Cook [Wed, 3 May 2017 18:46:30 +0000 (11:46 -0700)]
Merge pull request #10 from sifive/axi-mmio

axi4: switch to new pipelined converters

2 years agoMerge pull request #11 from sifive/spi
Yunsup Lee [Tue, 2 May 2017 21:36:39 +0000 (14:36 -0700)]
Merge pull request #11 from sifive/spi

SPI errata fixes

2 years agospi: Fix off-by-one error in calculating cycles per data frame
Albert Ou [Tue, 2 May 2017 19:35:34 +0000 (12:35 -0700)]
spi: Fix off-by-one error in calculating cycles per data frame

Issue: Configuring the frame length to certain values causes incorrect
operation.

Symptoms: Certain frame lengths result in the master sending one extra
clock pulse.  The slave device may then become desynchronized.

Workaround: The following frame lengths are supported and can be used.
Do not use other frame lengths.
* Serial mode: 0, 2, 4, 6, 8
* Dual mode:   0, 1, 3, 5, 7, 8
* Quad mode:   0, 1, 2, 3, 5, 6, 7, 8

2 years agospi: Fix io.port.dq(3) output enable
Albert Ou [Tue, 2 May 2017 19:07:37 +0000 (12:07 -0700)]
spi: Fix io.port.dq(3) output enable

Issue: The output enable signal for DQ[3] is not driven properly.

Symptoms: Output data from master to slave is not properly transmitted
in quad mode.  Data received from the slave is unaffected.

Workaround: When interfacing with SPI flash devices, do not use the
"Quad Input/Output Fast Read" command (opcode 0xEB) while in the
Extended SPI protocol.  Do not use the Native Quad SPI protocol.

2 years agoaxi4: switch to new pipelined converters axi-mmio
Wesley W. Terpstra [Wed, 26 Apr 2017 20:10:50 +0000 (13:10 -0700)]
axi4: switch to new pipelined converters

2 years agoMerge pull request #9 from sifive/vc707_mig_analog_inout
Henry Styles [Tue, 25 Apr 2017 17:18:46 +0000 (10:18 -0700)]
Merge pull request #9 from sifive/vc707_mig_analog_inout

Use _chisel3 analog for MIG inout

2 years agoUse _chisel3 analog for MIG inout vc707_mig_analog_inout
Henry Styles [Tue, 25 Apr 2017 17:15:00 +0000 (10:15 -0700)]
Use _chisel3 analog for MIG inout

2 years agoAdded stall for read after write (#8)
solomatnikov [Tue, 25 Apr 2017 16:14:00 +0000 (09:14 -0700)]
Added stall for read after write (#8)

2 years agoMerge pull request #7 from sifive/ndreset
Megan Wachs [Mon, 10 Apr 2017 21:25:08 +0000 (14:25 -0700)]
Merge pull request #7 from sifive/ndreset

MockAON: Accept the non-debug interrupt as an input to overall reset.

2 years agoMockAON: Accept the non-debug interrupt as an input to overall reset.
Megan Wachs [Fri, 7 Apr 2017 23:42:32 +0000 (16:42 -0700)]
MockAON: Accept the non-debug interrupt as an input to overall reset.

2 years agoMerge pull request #6 from sifive/debug_v013
Megan Wachs [Fri, 31 Mar 2017 22:14:35 +0000 (15:14 -0700)]
Merge pull request #6 from sifive/debug_v013

Debug v013

2 years agospi: correct polarity of FIRRTL combo loop detection workaround.
Megan Wachs [Fri, 31 Mar 2017 20:49:34 +0000 (13:49 -0700)]
spi: correct polarity of FIRRTL combo loop detection workaround.

2 years agoMerge remote-tracking branch 'origin/fix-false-comb-loop' into HEAD
Megan Wachs [Fri, 31 Mar 2017 03:01:30 +0000 (20:01 -0700)]
Merge remote-tracking branch 'origin/fix-false-comb-loop' into HEAD

2 years ago"Fix" false combinational loop through SPIArbiter fix-false-comb-loop
Jack Koenig [Fri, 31 Mar 2017 02:12:15 +0000 (19:12 -0700)]
"Fix" false combinational loop through SPIArbiter

Mux1H converts aggregates to UInt, muxes, then converts back which can
look like a cominational loop.

2 years agoMerge remote-tracking branch 'origin/master' into debug-0.13
Megan Wachs [Tue, 28 Mar 2017 01:48:24 +0000 (18:48 -0700)]
Merge remote-tracking branch 'origin/master' into debug-0.13

2 years agorename l2FrontendBus as fsb
Yunsup Lee [Sat, 25 Mar 2017 04:38:31 +0000 (21:38 -0700)]
rename l2FrontendBus as fsb

2 years agorename l2FrontendBus as fsb
Yunsup Lee [Sat, 25 Mar 2017 04:38:31 +0000 (21:38 -0700)]
rename l2FrontendBus as fsb