sifive-blocks.git
2017-08-18 Shreesha SrinathMerge pull request #34 from ss2783/master
2017-08-18 Shreesha SrinathRenamed ShiftReg to ShiftRegister
2017-08-18 Shreesha SrinathUpdates to go with the fpga-shells directory
2017-08-10 Wesley W. Terpstrauart: make it easy to simulate large text printouts...
2017-08-04 Shreesha SrinathMerge pull request #31 from ss2783/fix-mockaon
2017-08-03 Shreesha Srinathmockaon: Adds logic to detect external rtc toggles
2017-08-02 Albert OuMerge pull request #30 from sifive/spi
2017-08-02 Albert Ouspi: Fix invalid D channel response when flash interfac...
2017-08-02 Henry Cookallow bundle content params to be specified via a def...
2017-07-26 Wesley W. Terpstraspi: remove removed sink arg
2017-07-25 Yunsup LeeMerge pull request #27 from sifive/typed_pad_ctrl
2017-07-25 Yunsup Leemockaon: rename pads to pins
2017-07-25 Megan WachsPorts: Rename the 'fromXYZPort' to 'fromPort' since...
2017-07-25 Megan WachsMerge remote-tracking branch 'origin/master' into typed...
2017-07-25 Yunsup Leeuart: use PeripheryBusParams.frequency to calculate...
2017-07-24 Megan WachsMerge remote-tracking branch 'origin/master' into typed...
2017-07-23 Henry Cookperiphery: peripherals now in coreplex (#26)
2017-07-20 Megan Wachsgpio: Add missing file
2017-07-20 Megan WachsAdd missing cloneType methods to pin bundles
2017-07-20 Megan Wachsi2c: Remove pluralization on the bundle name, i2c not...
2017-07-19 Megan WachsRemove pluralization on interface names. Require clocks...
2017-07-19 Megan WachsMake it possible to adjust the type of pad controls...
2017-07-07 Henry CookRefactor package hierarchy. (#25)
2017-06-30 Wesley W. Terpstravc707 axi enhancements (#24)
2017-06-29 Wesley W. Terpstramig: fix MemoryDevice to use 'reg' properly
2017-06-29 Wesley W. Terpstraspi: include mem region (#23)
2017-06-29 Wesley W. Terpstradiplomacy: add reg-names to devices (#22)
2017-06-19 Megan Wachsgpio: Make IOF optional (#21)
2017-06-15 Henry Cookmake some base bundle classes easier to clone (#20)
2017-06-15 Wesley W. Terpstraspi: add dts ranges field for memory mapped spi (#19)
2017-06-13 Henry CookMerge pull request #18 from sifive/lazy-raw-module-imp
2017-06-13 Megan WachsMore Peripheral-to-pins cleanups
2017-06-13 Megan WachsUART: actually return the pins, not just the module...
2017-06-13 Megan WachsGPIO/SPI/I2C: Add sync stages in place of dummy variabl...
2017-06-13 Megan WachsGPIO/SPI/I2C: Add sync stages in place of dummy variabl...
2017-06-12 Henry Cookperiphery: convert periphery bundle traits to work...
2017-06-10 Megan WachsMerge pull request #17 from sifive/peripheral_options
2017-06-09 Megan Wachsperipheral_options: Actually compiles
2017-06-08 Megan WachsSPIFlash: make it listable
2017-06-08 Megan WachsGPIO: Make GPIO peripheral another listable one
2017-06-02 Wesley W. Terpstravc707axi: track rocketchip API changes (#16)
2017-05-14 Wesley W. Terpstrauart: power-on with the right divider for the design...
2017-05-13 Wesley W. TerpstraMerge pull request #14 from sifive/async-pcie
2017-05-13 Wesley W. Terpstravc707mig: use an external ibuf
2017-05-13 Wesley W. Terpstraxilinxvc707pciex1: push to a dedicated clock domain
2017-05-11 Wesley W. Terpstraxilinx mig: put a buffer infront of the controller...
2017-05-08 Wesley W. Terpstraxilinxvc707pciex1: better wrapper for AXI4-Lite control...
2017-05-03 Henry CookMerge pull request #10 from sifive/axi-mmio
2017-05-02 Yunsup LeeMerge pull request #11 from sifive/spi
2017-05-02 Albert Ouspi: Fix off-by-one error in calculating cycles per...
2017-05-02 Albert Ouspi: Fix io.port.dq(3) output enable
2017-04-26 Wesley W. Terpstraaxi4: switch to new pipelined converters axi-mmio
2017-04-25 Henry StylesMerge pull request #9 from sifive/vc707_mig_analog_inout
2017-04-25 Henry StylesUse _chisel3 analog for MIG inout vc707_mig_analog_inout
2017-04-25 solomatnikovAdded stall for read after write (#8)
2017-04-10 Megan WachsMerge pull request #7 from sifive/ndreset
2017-04-07 Megan WachsMockAON: Accept the non-debug interrupt as an input...
2017-03-31 Megan WachsMerge pull request #6 from sifive/debug_v013
2017-03-31 Megan Wachsspi: correct polarity of FIRRTL combo loop detection...
2017-03-31 Megan WachsMerge remote-tracking branch 'origin/fix-false-comb...
2017-03-31 Jack Koenig"Fix" false combinational loop through SPIArbiter fix-false-comb-loop
2017-03-28 Megan WachsMerge remote-tracking branch 'origin/master' into debug...
2017-03-26 Yunsup Leerename l2FrontendBus as fsb
2017-03-25 Yunsup Leerename l2FrontendBus as fsb
2017-03-25 Megan WachsJTAG: make TRSTn optional for all helpers as well to...
2017-03-23 Megan WachsMerge remote-tracking branch 'origin/master' into debug...
2017-03-22 Yunsup Leeupdate TLRegisterNode to take Seq of AddressSet
2017-03-22 Megan WachsTLSPI: address parameter must now be a sequence.
2017-03-14 Megan WachsAdjust JTAG for rocket-chip changes
2017-03-10 Megan WachsMerge remote-tracking branch 'origin/master' into debug...
2017-03-03 Wesley W. Terpstraxilinx pcie: add the high PCIe address bits (physical...
2017-03-03 Wesley W. TerpstraMerge pull request #4 from sifive/periphery-keys
2017-03-03 Wesley W. Terpstradevices: include DTS meta-data
2017-03-03 Wesley W. Terpstradevices: create periphery keys for all devices
2017-03-02 Megan Wachsjtag: The jtag interfaces have moved to a different...
2017-02-17 Megan WachsMerge pull request #2 from sifive/homogenous_bag_periph...
2017-02-17 Megan WachsUse HomogenousBag to handle lists of peripherals
2017-02-10 solomatnikovMerge pull request #1 from sifive/i2c
2017-02-10 Alex SolomatnikovMerge remote-tracking branch 'origin/master' into i2c i2c
2017-02-09 Alex SolomatnikovFlipped polarity of output enables to match Guava pins...
2017-02-09 Alex SolomatnikovMade regs 32-bit word aligned to match the rest of...
2017-02-08 Alex SolomatnikovAdded note: WISHBONE interface replaced by Tilelink2
2017-02-07 Alex SolomatnikovAdded license
2017-02-06 Alex SolomatnikovRenamed i2cDevices to i2c
2017-02-04 Wesley W. Terpstraxilinx mig: track changes in rocket-chip
2017-02-04 Alex SolomatnikovAddressing comments: bool style, comments, removed...
2017-02-04 Alex SolomatnikovBug fixes: passing OC WB test
2017-02-01 Wesley W. Terpstrasifive-blocks: trust diplomacy to get names right
2017-02-01 Alex SolomatnikovCompleted Chisel RTL (not tested yet)
2017-01-31 Wesley W. Terpstraspi: work around ucb-bar/chisel3#472
2017-01-30 Wesley W. Terpstraxilinx ip: adjust to new diplomacy API
2017-01-24 Alex SolomatnikovInitial (compilable) version of I2C (no actual logic...
2017-01-21 Wesley W. Terpstraxilinx pcie: put buffers before the outputs to the...
2017-01-20 Wesley W. Terpstramig: track change to Blind port API in rocket
2016-12-07 Wesley W. TerpstraLazyModule: provide Parameters
2016-12-07 Wesley W. Terpstraxilinx pcie: bytes, not bits
2016-12-03 Wesley W. TerpstraRegMapFIFO: amoor.w can do thread-safe TX
2016-11-30 Richard XiaAdd /target to .gitignore.
2016-11-29 SiFiveInitial commit.