src/soc/decoder/power_decoder2.py

   1 """Power ISA Decoder second stage
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
   6 over-riding the internal opcode when an exception is needed.
   7 """
   8
   9 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
  10 from nmigen.cli import rtlil
  11 from nmutil.util import sel
  12
  13 from soc.regfile.regfiles import XERRegs
  14
  15 from nmutil.picker import PriorityPicker
  16 from nmutil.iocontrol import RecordObject
  17 from nmutil.extend import exts
  18
  19 from soc.experiment.mem_types import LDSTException
  20
  21 from soc.decoder.power_svp64_prefix import SVP64PrefixDecoder
  22 from soc.decoder.power_svp64_extra import SVP64CRExtra, SVP64RegExtra
  23 from soc.decoder.power_regspec_map import regspec_decode_read
  24 from soc.decoder.power_regspec_map import regspec_decode_write
  25 from soc.decoder.power_decoder import create_pdecode
  26 from soc.decoder.power_enums import (MicrOp, CryIn, Function,
  27                                      CRInSel, CROutSel,
  28                                      LdstLen, In1Sel, In2Sel, In3Sel,
  29                                      OutSel, SPR, RC, LDSTMode,
  30                                      SVEXTRA, SVEtype)
  31 from soc.decoder.decode2execute1 import (Decode2ToExecute1Type, Data,
  32                                          Decode2ToOperand)
  33 from soc.sv.svp64 import SVP64Rec
  34 from soc.consts import (MSR, SPEC, EXTRA2, EXTRA3, SVP64P, field,
  35                         SPEC_SIZE, SPECb, SPEC_AUG_SIZE, SVP64CROffs)
  36
  37 from soc.regfile.regfiles import FastRegs
  38 from soc.consts import TT
  39 from soc.config.state import CoreState
  40 from soc.regfile.util import spr_to_fast
  41
  42
  43 def decode_spr_num(spr):
  44     return Cat(spr[5:10], spr[0:5])
  45
  46
  47 def instr_is_priv(m, op, insn):
  48     """determines if the instruction is privileged or not
  49     """
  50     comb = m.d.comb
  51     is_priv_insn = Signal(reset_less=True)
  52     with m.Switch(op):
  53         with m.Case(MicrOp.OP_ATTN, MicrOp.OP_MFMSR, MicrOp.OP_MTMSRD,
  54                     MicrOp.OP_MTMSR, MicrOp.OP_RFID):
  55             comb += is_priv_insn.eq(1)
  56         with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
  57         with m.Case(MicrOp.OP_MFSPR, MicrOp.OP_MTSPR):
  58             with m.If(insn[20]):  # field XFX.spr[-1] i think
  59                 comb += is_priv_insn.eq(1)
  60     return is_priv_insn
  61
  62
  63 class SPRMap(Elaboratable):
  64     """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
  65     """
  66
  67     def __init__(self):
  68         self.spr_i = Signal(10, reset_less=True)
  69         self.spr_o = Data(SPR, name="spr_o")
  70         self.fast_o = Data(3, name="fast_o")
  71
  72     def elaborate(self, platform):
  73         m = Module()
  74         with m.Switch(self.spr_i):
  75             for i, x in enumerate(SPR):
  76                 with m.Case(x.value):
  77                     m.d.comb += self.spr_o.data.eq(i)
  78                     m.d.comb += self.spr_o.ok.eq(1)
  79             for x, v in spr_to_fast.items():
  80                 with m.Case(x.value):
  81                     m.d.comb += self.fast_o.data.eq(v)
  82                     m.d.comb += self.fast_o.ok.eq(1)
  83         return m
  84
  85
  86 class DecodeA(Elaboratable):
  87     """DecodeA from instruction
  88
  89     decodes register RA, implicit and explicit CSRs
  90     """
  91
  92     def __init__(self, dec):
  93         self.dec = dec
  94         self.sel_in = Signal(In1Sel, reset_less=True)
  95         self.insn_in = Signal(32, reset_less=True)
  96         self.reg_out = Data(5, name="reg_a")
  97         self.spr_out = Data(SPR, "spr_a")
  98         self.fast_out = Data(3, "fast_a")
  99         self.sv_nz = Signal(1)
 100
 101     def elaborate(self, platform):
 102         m = Module()
 103         comb = m.d.comb
 104         op = self.dec.op
 105         reg = self.reg_out
 106         m.submodules.sprmap = sprmap = SPRMap()
 107
 108         # select Register A field, if *full 7 bits* are zero (2 more from SVP64)
 109         ra = Signal(5, reset_less=True)
 110         comb += ra.eq(self.dec.RA)
 111         with m.If((self.sel_in == In1Sel.RA) |
 112                   ((self.sel_in == In1Sel.RA_OR_ZERO) &
 113                    ((ra != Const(0, 5)) | (self.sv_nz != Const(0, 1))))):
 114             comb += reg.data.eq(ra)
 115             comb += reg.ok.eq(1)
 116
 117         # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
 118         # moved it to 1st position (in1_sel)... because
 119         rs = Signal(5, reset_less=True)
 120         comb += rs.eq(self.dec.RS)
 121         with m.If(self.sel_in == In1Sel.RS):
 122             comb += reg.data.eq(rs)
 123             comb += reg.ok.eq(1)
 124
 125         # decode Fast-SPR based on instruction type
 126         with m.Switch(op.internal_op):
 127
 128             # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
 129             with m.Case(MicrOp.OP_BC):
 130                 with m.If(~self.dec.BO[2]):  # 3.0B p38 BO2=0, use CTR reg
 131                     # constant: CTR
 132                     comb += self.fast_out.data.eq(FastRegs.CTR)
 133                     comb += self.fast_out.ok.eq(1)
 134             with m.Case(MicrOp.OP_BCREG):
 135                 xo9 = self.dec.FormXL.XO[9]  # 3.0B p38 top bit of XO
 136                 xo5 = self.dec.FormXL.XO[5]  # 3.0B p38
 137                 with m.If(xo9 & ~xo5):
 138                     # constant: CTR
 139                     comb += self.fast_out.data.eq(FastRegs.CTR)
 140                     comb += self.fast_out.ok.eq(1)
 141
 142             # MFSPR move from SPRs
 143             with m.Case(MicrOp.OP_MFSPR):
 144                 spr = Signal(10, reset_less=True)
 145                 comb += spr.eq(decode_spr_num(self.dec.SPR))  # from XFX
 146                 comb += sprmap.spr_i.eq(spr)
 147                 comb += self.spr_out.eq(sprmap.spr_o)
 148                 comb += self.fast_out.eq(sprmap.fast_o)
 149
 150         return m
 151
 152
 153 class DecodeAImm(Elaboratable):
 154     """DecodeA immediate from instruction
 155
 156     decodes register RA, whether immediate-zero, implicit and
 157     explicit CSRs.  SVP64 mode requires 2 extra bits
 158     """
 159
 160     def __init__(self, dec):
 161         self.dec = dec
 162         self.sel_in = Signal(In1Sel, reset_less=True)
 163         self.immz_out = Signal(reset_less=True)
 164         self.sv_nz = Signal(1) # EXTRA bits from SVP64
 165
 166     def elaborate(self, platform):
 167         m = Module()
 168         comb = m.d.comb
 169
 170         # zero immediate requested
 171         ra = Signal(5, reset_less=True)
 172         comb += ra.eq(self.dec.RA)
 173         with m.If((self.sel_in == In1Sel.RA_OR_ZERO) &
 174                     (ra == Const(0, 5)) &
 175                     (self.sv_nz == Const(0, 1))):
 176             comb += self.immz_out.eq(1)
 177
 178         return m
 179
 180
 181 class DecodeB(Elaboratable):
 182     """DecodeB from instruction
 183
 184     decodes register RB, different forms of immediate (signed, unsigned),
 185     and implicit SPRs.  register B is basically "lane 2" into the CompUnits.
 186     by industry-standard convention, "lane 2" is where fully-decoded
 187     immediates are muxed in.
 188     """
 189
 190     def __init__(self, dec):
 191         self.dec = dec
 192         self.sel_in = Signal(In2Sel, reset_less=True)
 193         self.insn_in = Signal(32, reset_less=True)
 194         self.reg_out = Data(7, "reg_b")
 195         self.reg_isvec = Signal(1, name="reg_b_isvec") # TODO: in reg_out
 196         self.fast_out = Data(3, "fast_b")
 197
 198     def elaborate(self, platform):
 199         m = Module()
 200         comb = m.d.comb
 201         op = self.dec.op
 202         reg = self.reg_out
 203
 204         # select Register B field
 205         with m.Switch(self.sel_in):
 206             with m.Case(In2Sel.RB):
 207                 comb += reg.data.eq(self.dec.RB)
 208                 comb += reg.ok.eq(1)
 209             with m.Case(In2Sel.RS):
 210                 # for M-Form shiftrot
 211                 comb += reg.data.eq(self.dec.RS)
 212                 comb += reg.ok.eq(1)
 213
 214         # decode SPR2 based on instruction type
 215         # BCREG implicitly uses LR or TAR for 2nd reg
 216         # CTR however is already in fast_spr1 *not* 2.
 217         with m.If(op.internal_op == MicrOp.OP_BCREG):
 218             xo9 = self.dec.FormXL.XO[9]  # 3.0B p38 top bit of XO
 219             xo5 = self.dec.FormXL.XO[5]  # 3.0B p38
 220             with m.If(~xo9):
 221                 comb += self.fast_out.data.eq(FastRegs.LR)
 222                 comb += self.fast_out.ok.eq(1)
 223             with m.Elif(xo5):
 224                 comb += self.fast_out.data.eq(FastRegs.TAR)
 225                 comb += self.fast_out.ok.eq(1)
 226
 227         return m
 228
 229
 230 class DecodeBImm(Elaboratable):
 231     """DecodeB immediate from instruction
 232     """
 233     def __init__(self, dec):
 234         self.dec = dec
 235         self.sel_in = Signal(In2Sel, reset_less=True)
 236         self.imm_out = Data(64, "imm_b")
 237
 238     def elaborate(self, platform):
 239         m = Module()
 240         comb = m.d.comb
 241
 242         # select Register B Immediate
 243         with m.Switch(self.sel_in):
 244             with m.Case(In2Sel.CONST_UI): # unsigned
 245                 comb += self.imm_out.data.eq(self.dec.UI)
 246                 comb += self.imm_out.ok.eq(1)
 247             with m.Case(In2Sel.CONST_SI):  # sign-extended 16-bit
 248                 si = Signal(16, reset_less=True)
 249                 comb += si.eq(self.dec.SI)
 250                 comb += self.imm_out.data.eq(exts(si, 16, 64))
 251                 comb += self.imm_out.ok.eq(1)
 252             with m.Case(In2Sel.CONST_SI_HI):  # sign-extended 16+16=32 bit
 253                 si_hi = Signal(32, reset_less=True)
 254                 comb += si_hi.eq(self.dec.SI << 16)
 255                 comb += self.imm_out.data.eq(exts(si_hi, 32, 64))
 256                 comb += self.imm_out.ok.eq(1)
 257             with m.Case(In2Sel.CONST_UI_HI): # unsigned
 258                 ui = Signal(16, reset_less=True)
 259                 comb += ui.eq(self.dec.UI)
 260                 comb += self.imm_out.data.eq(ui << 16)
 261                 comb += self.imm_out.ok.eq(1)
 262             with m.Case(In2Sel.CONST_LI): # sign-extend 24+2=26 bit
 263                 li = Signal(26, reset_less=True)
 264                 comb += li.eq(self.dec.LI << 2)
 265                 comb += self.imm_out.data.eq(exts(li, 26, 64))
 266                 comb += self.imm_out.ok.eq(1)
 267             with m.Case(In2Sel.CONST_BD): # sign-extend (14+2)=16 bit
 268                 bd = Signal(16, reset_less=True)
 269                 comb += bd.eq(self.dec.BD << 2)
 270                 comb += self.imm_out.data.eq(exts(bd, 16, 64))
 271                 comb += self.imm_out.ok.eq(1)
 272             with m.Case(In2Sel.CONST_DS): # sign-extended (14+2=16) bit
 273                 ds = Signal(16, reset_less=True)
 274                 comb += ds.eq(self.dec.DS << 2)
 275                 comb += self.imm_out.data.eq(exts(ds, 16, 64))
 276                 comb += self.imm_out.ok.eq(1)
 277             with m.Case(In2Sel.CONST_M1): # signed (-1)
 278                 comb += self.imm_out.data.eq(~Const(0, 64))  # all 1s
 279                 comb += self.imm_out.ok.eq(1)
 280             with m.Case(In2Sel.CONST_SH): # unsigned - for shift
 281                 comb += self.imm_out.data.eq(self.dec.sh)
 282                 comb += self.imm_out.ok.eq(1)
 283             with m.Case(In2Sel.CONST_SH32): # unsigned - for shift
 284                 comb += self.imm_out.data.eq(self.dec.SH32)
 285                 comb += self.imm_out.ok.eq(1)
 286
 287         return m
 288
 289
 290 class DecodeC(Elaboratable):
 291     """DecodeC from instruction
 292
 293     decodes register RC.  this is "lane 3" into some CompUnits (not many)
 294     """
 295
 296     def __init__(self, dec):
 297         self.dec = dec
 298         self.sel_in = Signal(In3Sel, reset_less=True)
 299         self.insn_in = Signal(32, reset_less=True)
 300         self.reg_out = Data(5, "reg_c")
 301
 302     def elaborate(self, platform):
 303         m = Module()
 304         comb = m.d.comb
 305         op = self.dec.op
 306         reg = self.reg_out
 307
 308         # select Register C field
 309         with m.Switch(self.sel_in):
 310             with m.Case(In3Sel.RB):
 311                 # for M-Form shiftrot
 312                 comb += reg.data.eq(self.dec.RB)
 313                 comb += reg.ok.eq(1)
 314             with m.Case(In3Sel.RS):
 315                 comb += reg.data.eq(self.dec.RS)
 316                 comb += reg.ok.eq(1)
 317
 318         return m
 319
 320
 321 class DecodeOut(Elaboratable):
 322     """DecodeOut from instruction
 323
 324     decodes output register RA, RT or SPR
 325     """
 326
 327     def __init__(self, dec):
 328         self.dec = dec
 329         self.sel_in = Signal(OutSel, reset_less=True)
 330         self.insn_in = Signal(32, reset_less=True)
 331         self.reg_out = Data(5, "reg_o")
 332         self.spr_out = Data(SPR, "spr_o")
 333         self.fast_out = Data(3, "fast_o")
 334
 335     def elaborate(self, platform):
 336         m = Module()
 337         comb = m.d.comb
 338         m.submodules.sprmap = sprmap = SPRMap()
 339         op = self.dec.op
 340         reg = self.reg_out
 341
 342         # select Register out field
 343         with m.Switch(self.sel_in):
 344             with m.Case(OutSel.RT):
 345                 comb += reg.data.eq(self.dec.RT)
 346                 comb += reg.ok.eq(1)
 347             with m.Case(OutSel.RA):
 348                 comb += reg.data.eq(self.dec.RA)
 349                 comb += reg.ok.eq(1)
 350             with m.Case(OutSel.SPR):
 351                 spr = Signal(10, reset_less=True)
 352                 comb += spr.eq(decode_spr_num(self.dec.SPR))  # from XFX
 353                 # MFSPR move to SPRs - needs mapping
 354                 with m.If(op.internal_op == MicrOp.OP_MTSPR):
 355                     comb += sprmap.spr_i.eq(spr)
 356                     comb += self.spr_out.eq(sprmap.spr_o)
 357                     comb += self.fast_out.eq(sprmap.fast_o)
 358
 359         # determine Fast Reg
 360         with m.Switch(op.internal_op):
 361
 362             # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
 363             with m.Case(MicrOp.OP_BC, MicrOp.OP_BCREG):
 364                 with m.If(~self.dec.BO[2]):  # 3.0B p38 BO2=0, use CTR reg
 365                     # constant: CTR
 366                     comb += self.fast_out.data.eq(FastRegs.CTR)
 367                     comb += self.fast_out.ok.eq(1)
 368
 369             # RFID 1st spr (fast)
 370             with m.Case(MicrOp.OP_RFID):
 371                 comb += self.fast_out.data.eq(FastRegs.SRR0)  # constant: SRR0
 372                 comb += self.fast_out.ok.eq(1)
 373
 374         return m
 375
 376
 377 class DecodeOut2(Elaboratable):
 378     """DecodeOut2 from instruction
 379
 380     decodes output registers (2nd one).  note that RA is *implicit* below,
 381     which now causes problems with SVP64
 382
 383     TODO: SVP64 is a little more complex, here.  svp64 allows extending
 384     by one more destination by having one more EXTRA field.  RA-as-src
 385     is not the same as RA-as-dest.  limited in that it's the same first
 386     5 bits (from the v3.0B opcode), but still kinda cool.  mostly used
 387     for operations that have src-as-dest: mostly this is LD/ST-with-update
 388     but there are others.
 389     """
 390
 391     def __init__(self, dec):
 392         self.dec = dec
 393         self.sel_in = Signal(OutSel, reset_less=True)
 394         self.lk = Signal(reset_less=True)
 395         self.insn_in = Signal(32, reset_less=True)
 396         self.reg_out = Data(5, "reg_o2")
 397         self.fast_out = Data(3, "fast_o2")
 398
 399     def elaborate(self, platform):
 400         m = Module()
 401         comb = m.d.comb
 402         op = self.dec.op
 403         #m.submodules.svdec = svdec = SVP64RegExtra()
 404
 405         # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
 406         #reg = Signal(5, reset_less=True)
 407
 408         if hasattr(self.dec.op, "upd"):
 409             # update mode LD/ST uses read-reg A also as an output
 410             with m.If(self.dec.op.upd == LDSTMode.update):
 411                 comb += self.reg_out.data.eq(self.dec.RA)
 412                 comb += self.reg_out.ok.eq(1)
 413
 414         # B, BC or BCREG: potential implicit register (LR) output
 415         # these give bl, bcl, bclrl, etc.
 416         with m.Switch(op.internal_op):
 417
 418             # BC* implicit register (LR)
 419             with m.Case(MicrOp.OP_BC, MicrOp.OP_B, MicrOp.OP_BCREG):
 420                 with m.If(self.lk):  # "link" mode
 421                     comb += self.fast_out.data.eq(FastRegs.LR)  # constant: LR
 422                     comb += self.fast_out.ok.eq(1)
 423
 424             # RFID 2nd spr (fast)
 425             with m.Case(MicrOp.OP_RFID):
 426                 comb += self.fast_out.data.eq(FastRegs.SRR1)  # constant: SRR1
 427                 comb += self.fast_out.ok.eq(1)
 428
 429         return m
 430
 431
 432 class DecodeRC(Elaboratable):
 433     """DecodeRc from instruction
 434
 435     decodes Record bit Rc
 436     """
 437
 438     def __init__(self, dec):
 439         self.dec = dec
 440         self.sel_in = Signal(RC, reset_less=True)
 441         self.insn_in = Signal(32, reset_less=True)
 442         self.rc_out = Data(1, "rc")
 443
 444     def elaborate(self, platform):
 445         m = Module()
 446         comb = m.d.comb
 447
 448         # select Record bit out field
 449         with m.Switch(self.sel_in):
 450             with m.Case(RC.RC):
 451                 comb += self.rc_out.data.eq(self.dec.Rc)
 452                 comb += self.rc_out.ok.eq(1)
 453             with m.Case(RC.ONE):
 454                 comb += self.rc_out.data.eq(1)
 455                 comb += self.rc_out.ok.eq(1)
 456             with m.Case(RC.NONE):
 457                 comb += self.rc_out.data.eq(0)
 458                 comb += self.rc_out.ok.eq(1)
 459
 460         return m
 461
 462
 463 class DecodeOE(Elaboratable):
 464     """DecodeOE from instruction
 465
 466     decodes OE field: uses RC decode detection which might not be good
 467
 468     -- For now, use "rc" in the decode table to decide whether oe exists.
 469     -- This is not entirely correct architecturally: For mulhd and
 470     -- mulhdu, the OE field is reserved. It remains to be seen what an
 471     -- actual POWER9 does if we set it on those instructions, for now we
 472     -- test that further down when assigning to the multiplier oe input.
 473     """
 474
 475     def __init__(self, dec):
 476         self.dec = dec
 477         self.sel_in = Signal(RC, reset_less=True)
 478         self.insn_in = Signal(32, reset_less=True)
 479         self.oe_out = Data(1, "oe")
 480
 481     def elaborate(self, platform):
 482         m = Module()
 483         comb = m.d.comb
 484         op = self.dec.op
 485
 486         with m.Switch(op.internal_op):
 487
 488             # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
 489             # also rotate
 490             # XXX ARGH! ignoring OE causes incompatibility with microwatt
 491             # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
 492             with m.Case(MicrOp.OP_MUL_H64, MicrOp.OP_MUL_H32,
 493                         MicrOp.OP_EXTS, MicrOp.OP_CNTZ,
 494                         MicrOp.OP_SHL, MicrOp.OP_SHR, MicrOp.OP_RLC,
 495                         MicrOp.OP_LOAD, MicrOp.OP_STORE,
 496                         MicrOp.OP_RLCL, MicrOp.OP_RLCR,
 497                         MicrOp.OP_EXTSWSLI):
 498                 pass
 499
 500             # all other ops decode OE field
 501             with m.Default():
 502                 # select OE bit out field
 503                 with m.Switch(self.sel_in):
 504                     with m.Case(RC.RC):
 505                         comb += self.oe_out.data.eq(self.dec.OE)
 506                         comb += self.oe_out.ok.eq(1)
 507
 508         return m
 509
 510
 511 class DecodeCRIn(Elaboratable):
 512     """Decodes input CR from instruction
 513
 514     CR indices - insn fields - (not the data *in* the CR) require only 3
 515     bits because they refer to CR0-CR7
 516     """
 517
 518     def __init__(self, dec):
 519         self.dec = dec
 520         self.sel_in = Signal(CRInSel, reset_less=True)
 521         self.insn_in = Signal(32, reset_less=True)
 522         self.cr_bitfield = Data(3, "cr_bitfield")
 523         self.cr_bitfield_b = Data(3, "cr_bitfield_b")
 524         self.cr_bitfield_o = Data(3, "cr_bitfield_o")
 525         self.whole_reg = Data(8,  "cr_fxm")
 526         self.sv_override = Signal(2, reset_less=True) # do not do EXTRA spec
 527
 528     def elaborate(self, platform):
 529         m = Module()
 530         comb = m.d.comb
 531         op = self.dec.op
 532         m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
 533                                                        reverse_o=True)
 534
 535         # zero-initialisation
 536         comb += self.cr_bitfield.ok.eq(0)
 537         comb += self.cr_bitfield_b.ok.eq(0)
 538         comb += self.cr_bitfield_o.ok.eq(0)
 539         comb += self.whole_reg.ok.eq(0)
 540         comb += self.sv_override.eq(0)
 541
 542         # select the relevant CR bitfields
 543         with m.Switch(self.sel_in):
 544             with m.Case(CRInSel.NONE):
 545                 pass  # No bitfield activated
 546             with m.Case(CRInSel.CR0):
 547                 comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering)
 548                 comb += self.cr_bitfield.ok.eq(1)
 549                 comb += self.sv_override.eq(1)
 550             with m.Case(CRInSel.CR1):
 551                 comb += self.cr_bitfield.data.eq(1) # CR1 (MSB0 numbering)
 552                 comb += self.cr_bitfield.ok.eq(1)
 553                 comb += self.sv_override.eq(2)
 554             with m.Case(CRInSel.BI):
 555                 comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
 556                 comb += self.cr_bitfield.ok.eq(1)
 557             with m.Case(CRInSel.BFA):
 558                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
 559                 comb += self.cr_bitfield.ok.eq(1)
 560             with m.Case(CRInSel.BA_BB):
 561                 comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
 562                 comb += self.cr_bitfield.ok.eq(1)
 563                 comb += self.cr_bitfield_b.data.eq(self.dec.BB[2:5])
 564                 comb += self.cr_bitfield_b.ok.eq(1)
 565                 comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
 566                 comb += self.cr_bitfield_o.ok.eq(1)
 567             with m.Case(CRInSel.BC):
 568                 comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
 569                 comb += self.cr_bitfield.ok.eq(1)
 570             with m.Case(CRInSel.WHOLE_REG):
 571                 comb += self.whole_reg.ok.eq(1)
 572                 move_one = Signal(reset_less=True)
 573                 comb += move_one.eq(self.insn_in[20]) # MSB0 bit 11
 574                 with m.If((op.internal_op == MicrOp.OP_MFCR) & move_one):
 575                     # must one-hot the FXM field
 576                     comb += ppick.i.eq(self.dec.FXM)
 577                     comb += self.whole_reg.data.eq(ppick.o)
 578                 with m.Else():
 579                     # otherwise use all of it
 580                     comb += self.whole_reg.data.eq(0xff)
 581
 582         return m
 583
 584
 585 class DecodeCROut(Elaboratable):
 586     """Decodes input CR from instruction
 587
 588     CR indices - insn fields - (not the data *in* the CR) require only 3
 589     bits because they refer to CR0-CR7
 590     """
 591
 592     def __init__(self, dec):
 593         self.dec = dec
 594         self.rc_in = Signal(reset_less=True)
 595         self.sel_in = Signal(CROutSel, reset_less=True)
 596         self.insn_in = Signal(32, reset_less=True)
 597         self.cr_bitfield = Data(3, "cr_bitfield")
 598         self.whole_reg = Data(8,  "cr_fxm")
 599         self.sv_override = Signal(2, reset_less=True) # do not do EXTRA spec
 600
 601     def elaborate(self, platform):
 602         m = Module()
 603         comb = m.d.comb
 604         op = self.dec.op
 605         m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
 606                                                        reverse_o=True)
 607
 608         comb += self.cr_bitfield.ok.eq(0)
 609         comb += self.whole_reg.ok.eq(0)
 610         comb += self.sv_override.eq(0)
 611
 612         # please note these MUST match (setting of cr_bitfield.ok) exactly
 613         # with write_cr0 below in PowerDecoder2.  the reason it's separated
 614         # is to avoid having duplicate copies of DecodeCROut in multiple
 615         # PowerDecoderSubsets.  register decoding should be a one-off in
 616         # PowerDecoder2.  see https://bugs.libre-soc.org/show_bug.cgi?id=606
 617
 618         with m.Switch(self.sel_in):
 619             with m.Case(CROutSel.NONE):
 620                 pass  # No bitfield activated
 621             with m.Case(CROutSel.CR0):
 622                 comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering)
 623                 comb += self.cr_bitfield.ok.eq(self.rc_in)  # only when RC=1
 624                 comb += self.sv_override.eq(1)
 625             with m.Case(CROutSel.CR1):
 626                 comb += self.cr_bitfield.data.eq(1) # CR1 (MSB0 numbering)
 627                 comb += self.cr_bitfield.ok.eq(self.rc_in)  # only when RC=1
 628                 comb += self.sv_override.eq(2)
 629             with m.Case(CROutSel.BF):
 630                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BF)
 631                 comb += self.cr_bitfield.ok.eq(1)
 632             with m.Case(CROutSel.BT):
 633                 comb += self.cr_bitfield.data.eq(self.dec.FormXL.BT[2:5])
 634                 comb += self.cr_bitfield.ok.eq(1)
 635             with m.Case(CROutSel.WHOLE_REG):
 636                 comb += self.whole_reg.ok.eq(1)
 637                 move_one = Signal(reset_less=True)
 638                 comb += move_one.eq(self.insn_in[20])
 639                 with m.If((op.internal_op == MicrOp.OP_MTCRF)):
 640                     with m.If(move_one):
 641                         # must one-hot the FXM field
 642                         comb += ppick.i.eq(self.dec.FXM)
 643                         with m.If(ppick.en_o):
 644                             comb += self.whole_reg.data.eq(ppick.o)
 645                         with m.Else():
 646                             comb += self.whole_reg.data.eq(0b00000001) # CR7
 647                     with m.Else():
 648                         comb += self.whole_reg.data.eq(self.dec.FXM)
 649                 with m.Else():
 650                     # otherwise use all of it
 651                     comb += self.whole_reg.data.eq(0xff)
 652
 653         return m
 654
 655 # dictionary of Input Record field names that, if they exist,
 656 # will need a corresponding CSV Decoder file column (actually, PowerOp)
 657 # to be decoded (this includes the single bit names)
 658 record_names = {'insn_type': 'internal_op',
 659                 'fn_unit': 'function_unit',
 660                 'rc': 'rc_sel',
 661                 'oe': 'rc_sel',
 662                 'zero_a': 'in1_sel',
 663                 'imm_data': 'in2_sel',
 664                 'invert_in': 'inv_a',
 665                 'invert_out': 'inv_out',
 666                 'rc': 'cr_out',
 667                 'oe': 'cr_in',
 668                 'output_carry': 'cry_out',
 669                 'input_carry': 'cry_in',
 670                 'is_32bit': 'is_32b',
 671                 'is_signed': 'sgn',
 672                 'lk': 'lk',
 673                 'data_len': 'ldst_len',
 674                 'byte_reverse': 'br',
 675                 'sign_extend': 'sgn_ext',
 676                 'ldst_mode': 'upd',
 677                 }
 678
 679
 680 class PowerDecodeSubset(Elaboratable):
 681     """PowerDecodeSubset: dynamic subset decoder
 682
 683     only fields actually requested are copied over. hence, "subset" (duh).
 684     """
 685     def __init__(self, dec, opkls=None, fn_name=None, final=False, state=None,
 686                             svp64_en=True):
 687
 688         self.svp64_en = svp64_en
 689         if svp64_en:
 690             self.sv_rm = SVP64Rec(name="dec_svp64") # SVP64 RM field
 691         self.sv_a_nz = Signal(1)
 692         self.final = final
 693         self.opkls = opkls
 694         self.fn_name = fn_name
 695         if opkls is None:
 696             opkls = Decode2ToOperand
 697         self.do = opkls(fn_name)
 698         col_subset = self.get_col_subset(self.do)
 699
 700         # only needed for "main" PowerDecode2
 701         if not self.final:
 702             self.e = Decode2ToExecute1Type(name=self.fn_name, do=self.do)
 703
 704         # create decoder if one not already given
 705         if dec is None:
 706             dec = create_pdecode(name=fn_name, col_subset=col_subset,
 707                                       row_subset=self.rowsubsetfn)
 708         self.dec = dec
 709
 710         # state information needed by the Decoder
 711         if state is None:
 712             state = CoreState("dec2")
 713         self.state = state
 714
 715     def get_col_subset(self, do):
 716         subset = { 'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
 717         for k, v in record_names.items():
 718             if hasattr(do, k):
 719                 subset.add(v)
 720         print ("get_col_subset", self.fn_name, do.fields, subset)
 721         return subset
 722
 723     def rowsubsetfn(self, opcode, row):
 724         """select per-Function-Unit subset of opcodes to be processed
 725
 726         normally this just looks at the "unit" column.  MMU is different
 727         in that it processes specific SPR set/get operations that the SPR
 728         pipeline should not.
 729         """
 730         return (row['unit'] == self.fn_name or
 731                 # sigh a dreadful hack: MTSPR and MFSPR need to be processed
 732                 # by the MMU pipeline so we direct those opcodes to MMU **AND**
 733                 # SPR pipelines, then selectively weed out the SPRs that should
 734                 # or should not not go to each pipeline, further down.
 735                 # really this should be done by modifying the CSV syntax
 736                 # to support multiple tasks (unit column multiple entries)
 737                 # see https://bugs.libre-soc.org/show_bug.cgi?id=310
 738                (self.fn_name == 'MMU' and row['unit'] == 'SPR' and
 739                 row['internal op'] in ['OP_MTSPR', 'OP_MFSPR'])
 740                 )
 741
 742     def ports(self):
 743         ports = self.dec.ports() + self.e.ports()
 744         if self.svp64_en:
 745             ports += self.sv_rm.ports()
 746         return ports
 747
 748     def needs_field(self, field, op_field):
 749         if self.final:
 750             do = self.do
 751         else:
 752             do = self.e_tmp.do
 753         return hasattr(do, field) and self.op_get(op_field) is not None
 754
 755     def do_copy(self, field, val, final=False):
 756         if final or self.final:
 757             do = self.do
 758         else:
 759             do = self.e_tmp.do
 760         if hasattr(do, field) and val is not None:
 761             return getattr(do, field).eq(val)
 762         return []
 763
 764     def op_get(self, op_field):
 765         return getattr(self.dec.op, op_field, None)
 766
 767     def elaborate(self, platform):
 768         m = Module()
 769         comb = m.d.comb
 770         state = self.state
 771         op, do = self.dec.op, self.do
 772         msr, cia = state.msr, state.pc
 773         # fill in for a normal instruction (not an exception)
 774         # copy over if non-exception, non-privileged etc. is detected
 775         if not self.final:
 776             if self.fn_name is None:
 777                 name = "tmp"
 778             else:
 779                 name = self.fn_name + "tmp"
 780             self.e_tmp = Decode2ToExecute1Type(name=name, opkls=self.opkls)
 781
 782         # set up submodule decoders
 783         m.submodules.dec = self.dec
 784         m.submodules.dec_rc = self.dec_rc = dec_rc = DecodeRC(self.dec)
 785         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
 786
 787         # copy instruction through...
 788         for i in [do.insn, dec_rc.insn_in, dec_oe.insn_in, ]:
 789             comb += i.eq(self.dec.opcode_in)
 790
 791         # ...and subdecoders' input fields
 792         comb += dec_rc.sel_in.eq(op.rc_sel)
 793         comb += dec_oe.sel_in.eq(op.rc_sel)  # XXX should be OE sel
 794
 795         # copy "state" over
 796         comb += self.do_copy("msr", msr)
 797         comb += self.do_copy("cia", cia)
 798
 799         # set up instruction type
 800         # no op: defaults to OP_ILLEGAL
 801         internal_op = self.op_get("internal_op")
 802         comb += self.do_copy("insn_type", internal_op)
 803
 804         # function unit for decoded instruction: requires minor redirect
 805         # for SPR set/get
 806         fn = self.op_get("function_unit")
 807         spr = Signal(10, reset_less=True)
 808         comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
 809
 810         # Microwatt doesn't implement the partition table
 811         # instead has PRTBL register (SPR) to point to process table
 812         is_spr_mv = Signal()
 813         is_mmu_spr = Signal()
 814         comb += is_spr_mv.eq((internal_op == MicrOp.OP_MTSPR) |
 815                              (internal_op == MicrOp.OP_MFSPR))
 816         comb += is_mmu_spr.eq((spr == SPR.DSISR.value) |
 817                               (spr == SPR.DAR.value) |
 818                               (spr == SPR.PRTBL.value) |
 819                               (spr == SPR.PIDR.value))
 820         # MMU must receive MMU SPRs
 821         with m.If(is_spr_mv & (fn == Function.SPR) & is_mmu_spr):
 822             comb += self.do_copy("fn_unit", Function.NONE)
 823             comb += self.do_copy("insn_type", MicrOp.OP_ILLEGAL)
 824         # SPR pipe must *not* receive MMU SPRs
 825         with m.Elif(is_spr_mv & (fn == Function.MMU) & ~is_mmu_spr):
 826             comb += self.do_copy("fn_unit", Function.NONE)
 827             comb += self.do_copy("insn_type", MicrOp.OP_ILLEGAL)
 828         # all others ok
 829         with m.Else():
 830             comb += self.do_copy("fn_unit", fn)
 831
 832         # immediates
 833         if self.needs_field("zero_a", "in1_sel"):
 834             m.submodules.dec_ai = dec_ai = DecodeAImm(self.dec)
 835             comb += dec_ai.sv_nz.eq(self.sv_a_nz)
 836             comb += dec_ai.sel_in.eq(op.in1_sel)
 837             comb += self.do_copy("zero_a", dec_ai.immz_out)  # RA==0 detected
 838         if self.needs_field("imm_data", "in2_sel"):
 839             m.submodules.dec_bi = dec_bi = DecodeBImm(self.dec)
 840             comb += dec_bi.sel_in.eq(op.in2_sel)
 841             comb += self.do_copy("imm_data", dec_bi.imm_out) # imm in RB
 842
 843         # rc and oe out
 844         comb += self.do_copy("rc", dec_rc.rc_out)
 845         comb += self.do_copy("oe", dec_oe.oe_out)
 846
 847         # CR in/out - note: these MUST match with what happens in
 848         # DecodeCROut!
 849         rc_out = self.dec_rc.rc_out.data
 850         with m.Switch(op.cr_out):
 851             with m.Case(CROutSel.CR0, CROutSel.CR1):
 852                 comb += self.do_copy("write_cr0", rc_out) # only when RC=1
 853             with m.Case(CROutSel.BF, CROutSel.BT):
 854                 comb += self.do_copy("write_cr0", 1)
 855
 856         comb += self.do_copy("input_cr", self.op_get("cr_in"))   # CR in
 857         comb += self.do_copy("output_cr", self.op_get("cr_out"))  # CR out
 858
 859         # decoded/selected instruction flags
 860         comb += self.do_copy("data_len", self.op_get("ldst_len"))
 861         comb += self.do_copy("invert_in", self.op_get("inv_a"))
 862         comb += self.do_copy("invert_out", self.op_get("inv_out"))
 863         comb += self.do_copy("input_carry", self.op_get("cry_in"))
 864         comb += self.do_copy("output_carry", self.op_get("cry_out"))
 865         comb += self.do_copy("is_32bit", self.op_get("is_32b"))
 866         comb += self.do_copy("is_signed", self.op_get("sgn"))
 867         lk = self.op_get("lk")
 868         if lk is not None:
 869             with m.If(lk):
 870                 comb += self.do_copy("lk", self.dec.LK)  # XXX TODO: accessor
 871
 872         comb += self.do_copy("byte_reverse", self.op_get("br"))
 873         comb += self.do_copy("sign_extend", self.op_get("sgn_ext"))
 874         comb += self.do_copy("ldst_mode", self.op_get("upd"))  # LD/ST mode
 875
 876         return m
 877
 878
 879 class PowerDecode2(PowerDecodeSubset):
 880     """PowerDecode2: the main instruction decoder.
 881
 882     whilst PowerDecode is responsible for decoding the actual opcode, this
 883     module encapsulates further specialist, sparse information and
 884     expansion of fields that is inconvenient to have in the CSV files.
 885     for example: the encoding of the immediates, which are detected
 886     and expanded out to their full value from an annotated (enum)
 887     representation.
 888
 889     implicit register usage is also set up, here.  for example: OP_BC
 890     requires implicitly reading CTR, OP_RFID requires implicitly writing
 891     to SRR1 and so on.
 892
 893     in addition, PowerDecoder2 is responsible for detecting whether
 894     instructions are illegal (or privileged) or not, and instead of
 895     just leaving at that, *replacing* the instruction to execute with
 896     a suitable alternative (trap).
 897
 898     LDSTExceptions are done the cycle _after_ they're detected (after
 899     they come out of LDSTCompUnit).  basically despite the instruction
 900     being decoded, the results of the decode are completely ignored
 901     and "exception.happened" used to set the "actual" instruction to
 902     "OP_TRAP".  the LDSTException data structure gets filled in,
 903     in the CompTrapOpSubset and that's what it fills in SRR.
 904
 905     to make this work, TestIssuer must notice "exception.happened"
 906     after the (failed) LD/ST and copies the LDSTException info from
 907     the output, into here (PowerDecoder2).  without incrementing PC.
 908     """
 909
 910     def __init__(self, dec, opkls=None, fn_name=None, final=False,
 911                             state=None, svp64_en=True):
 912         super().__init__(dec, opkls, fn_name, final, state, svp64_en)
 913         self.exc = LDSTException("dec2_exc")
 914
 915         if self.svp64_en:
 916             self.cr_out_isvec = Signal(1, name="cr_out_isvec")
 917             self.cr_in_isvec = Signal(1, name="cr_in_isvec")
 918             self.cr_in_b_isvec = Signal(1, name="cr_in_b_isvec")
 919             self.cr_in_o_isvec = Signal(1, name="cr_in_o_isvec")
 920             self.in1_isvec = Signal(1, name="reg_a_isvec")
 921             self.in2_isvec = Signal(1, name="reg_b_isvec")
 922             self.in3_isvec = Signal(1, name="reg_c_isvec")
 923             self.o_isvec = Signal(1, name="reg_o_isvec")
 924             self.o2_isvec = Signal(1, name="reg_o2_isvec")
 925             self.no_in_vec = Signal(1, name="no_in_vec") # no inputs vector
 926             self.no_out_vec = Signal(1, name="no_out_vec") # no outputs vector
 927         else:
 928             self.no_in_vec = Const(1, 1)
 929             self.no_out_vec = Const(1, 1)
 930
 931     def get_col_subset(self, opkls):
 932         subset = super().get_col_subset(opkls)
 933         subset.add("asmcode")
 934         subset.add("in1_sel")
 935         subset.add("in2_sel")
 936         subset.add("in3_sel")
 937         subset.add("out_sel")
 938         if self.svp64_en:
 939             subset.add("sv_in1")
 940             subset.add("sv_in2")
 941             subset.add("sv_in3")
 942             subset.add("sv_out")
 943             subset.add("sv_cr_in")
 944             subset.add("sv_cr_out")
 945             subset.add("SV_Etype")
 946             subset.add("SV_Ptype")
 947         subset.add("lk")
 948         subset.add("internal_op")
 949         subset.add("form")
 950         return subset
 951
 952     def elaborate(self, platform):
 953         m = super().elaborate(platform)
 954         comb = m.d.comb
 955         state = self.state
 956         e_out, op, do_out = self.e, self.dec.op, self.e.do
 957         dec_spr, msr, cia, ext_irq = state.dec, state.msr, state.pc, state.eint
 958         rc_out = self.dec_rc.rc_out.data
 959         e = self.e_tmp
 960         do = e.do
 961
 962         # fill in for a normal instruction (not an exception)
 963         # copy over if non-exception, non-privileged etc. is detected
 964
 965         # set up submodule decoders
 966         m.submodules.dec_a = dec_a = DecodeA(self.dec)
 967         m.submodules.dec_b = dec_b = DecodeB(self.dec)
 968         m.submodules.dec_c = dec_c = DecodeC(self.dec)
 969         m.submodules.dec_o = dec_o = DecodeOut(self.dec)
 970         m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
 971         m.submodules.dec_cr_in = self.dec_cr_in = DecodeCRIn(self.dec)
 972         m.submodules.dec_cr_out = self.dec_cr_out = DecodeCROut(self.dec)
 973         comb += dec_a.sv_nz.eq(self.sv_a_nz)
 974
 975         if self.svp64_en:
 976             # and SVP64 Extra decoders
 977             m.submodules.crout_svdec = crout_svdec = SVP64CRExtra()
 978             m.submodules.crin_svdec = crin_svdec = SVP64CRExtra()
 979             m.submodules.crin_svdec_b = crin_svdec_b = SVP64CRExtra()
 980             m.submodules.crin_svdec_o = crin_svdec_o = SVP64CRExtra()
 981             m.submodules.in1_svdec = in1_svdec = SVP64RegExtra()
 982             m.submodules.in2_svdec = in2_svdec = SVP64RegExtra()
 983             m.submodules.in3_svdec = in3_svdec = SVP64RegExtra()
 984             m.submodules.o_svdec = o_svdec = SVP64RegExtra()
 985             m.submodules.o2_svdec = o2_svdec = SVP64RegExtra()
 986
 987             # debug access to crout_svdec (used in get_pdecode_cr_out)
 988             self.crout_svdec = crout_svdec
 989
 990         # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
 991         reg = Signal(5, reset_less=True)
 992
 993         # copy instruction through...
 994         for i in [do.insn, dec_a.insn_in, dec_b.insn_in,
 995                   self.dec_cr_in.insn_in, self.dec_cr_out.insn_in,
 996                   dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in]:
 997             comb += i.eq(self.dec.opcode_in)
 998
 999         # CR setup
1000         comb += self.dec_cr_in.sel_in.eq(op.cr_in)
1001         comb += self.dec_cr_out.sel_in.eq(op.cr_out)
1002         comb += self.dec_cr_out.rc_in.eq(rc_out)
1003
1004         # CR register info
1005         comb += self.do_copy("read_cr_whole", self.dec_cr_in.whole_reg)
1006         comb += self.do_copy("write_cr_whole", self.dec_cr_out.whole_reg)
1007
1008         # ...and subdecoders' input fields
1009         comb += dec_a.sel_in.eq(op.in1_sel)
1010         comb += dec_b.sel_in.eq(op.in2_sel)
1011         comb += dec_c.sel_in.eq(op.in3_sel)
1012         comb += dec_o.sel_in.eq(op.out_sel)
1013         comb += dec_o2.sel_in.eq(op.out_sel)
1014         if hasattr(do, "lk"):
1015             comb += dec_o2.lk.eq(do.lk)
1016
1017         if self.svp64_en:
1018             # now do the SVP64 munging.  op.SV_Etype and op.sv_in1 comes from
1019             # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1020             # which in turn were auto-generated by sv_analysis.py
1021             extra = self.sv_rm.extra            # SVP64 extra bits 10:18
1022
1023             #######
1024             # CR out
1025             comb += crout_svdec.idx.eq(op.sv_cr_out)  # SVP64 CR out
1026             comb += self.cr_out_isvec.eq(crout_svdec.isvec)
1027
1028             #######
1029             # CR in - selection slightly different due to shared CR field sigh
1030             cr_a_idx = Signal(SVEXTRA)
1031             cr_b_idx = Signal(SVEXTRA)
1032
1033             # these change slightly, when decoding BA/BB.  really should have
1034             # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1035             comb += cr_a_idx.eq(op.sv_cr_in)
1036             comb += cr_b_idx.eq(SVEXTRA.NONE)
1037             with m.If(op.sv_cr_in == SVEXTRA.Idx_1_2.value):
1038                 comb += cr_a_idx.eq(SVEXTRA.Idx1)
1039                 comb += cr_b_idx.eq(SVEXTRA.Idx2)
1040
1041             comb += self.cr_in_isvec.eq(crin_svdec.isvec)
1042             comb += self.cr_in_b_isvec.eq(crin_svdec_b.isvec)
1043             comb += self.cr_in_o_isvec.eq(crin_svdec_o.isvec)
1044
1045             # indices are slightly different, BA/BB mess sorted above
1046             comb += crin_svdec.idx.eq(cr_a_idx)       # SVP64 CR in A
1047             comb += crin_svdec_b.idx.eq(cr_b_idx)     # SVP64 CR in B
1048             comb += crin_svdec_o.idx.eq(op.sv_cr_out) # SVP64 CR out
1049
1050             # get SVSTATE srcstep (TODO: elwidth, dststep etc.) needed below
1051             srcstep = Signal.like(self.state.svstate.srcstep)
1052             comb += srcstep.eq(self.state.svstate.srcstep)
1053
1054             # registers a, b, c and out and out2 (LD/ST EA)
1055             for to_reg, fromreg, svdec in (
1056                 (e.read_reg1, dec_a.reg_out, in1_svdec),
1057                 (e.read_reg2, dec_b.reg_out, in2_svdec),
1058                 (e.read_reg3, dec_c.reg_out, in3_svdec),
1059                 (e.write_reg, dec_o.reg_out, o_svdec),
1060                 (e.write_ea, dec_o2.reg_out, o2_svdec)):
1061                 comb += svdec.extra.eq(extra)        # EXTRA field of SVP64 RM
1062                 comb += svdec.etype.eq(op.SV_Etype)  # EXTRA2/3 for this insn
1063                 comb += svdec.reg_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
1064                 comb += to_reg.ok.eq(fromreg.ok)
1065                 # detect if Vectorised: add srcstep if yes.  TODO: a LOT.
1066                 # this trick only holds when elwidth=default and in single-pred
1067                 with m.If(svdec.isvec):
1068                     comb += to_reg.data.eq(srcstep+svdec.reg_out) # 7-bit output
1069                 with m.Else():
1070                     comb += to_reg.data.eq(svdec.reg_out) # 7-bit output
1071
1072             comb += in1_svdec.idx.eq(op.sv_in1)  # SVP64 reg #1 (in1_sel)
1073             comb += in2_svdec.idx.eq(op.sv_in2)  # SVP64 reg #2 (in2_sel)
1074             comb += in3_svdec.idx.eq(op.sv_in3)  # SVP64 reg #3 (in3_sel)
1075             comb += o_svdec.idx.eq(op.sv_out)    # SVP64 output (out_sel)
1076             # XXX TODO - work out where this should come from.  the problem is
1077             # that LD-with-update is implied (computed from "is instruction in
1078             # "update mode" rather than specified cleanly as its own CSV column
1079             #comb += o2_svdec.idx.eq(op.sv_out)    # SVP64 output (implicit)
1080
1081             # output reg-is-vectorised (and when no in/out is vectorised)
1082             comb += self.in1_isvec.eq(in1_svdec.isvec)
1083             comb += self.in2_isvec.eq(in2_svdec.isvec)
1084             comb += self.in3_isvec.eq(in3_svdec.isvec)
1085             comb += self.o_isvec.eq(o_svdec.isvec)
1086             comb += self.o2_isvec.eq(o2_svdec.isvec)
1087             # TODO add SPRs here.  must be True when *all* are scalar
1088             l = map(lambda svdec: svdec.isvec, [in1_svdec, in2_svdec, in3_svdec,
1089                                         crin_svdec, crin_svdec_b, crin_svdec_o])
1090             comb += self.no_in_vec.eq(~Cat(*l).bool()) # all input scalar
1091             l = map(lambda svdec: svdec.isvec, [o2_svdec, o_svdec, crout_svdec])
1092             comb += self.no_out_vec.eq(~Cat(*l).bool()) # all output scalar
1093
1094             # condition registers (CR)
1095             for to_reg, cr, name, svdec in (
1096                 (e.read_cr1, self.dec_cr_in, "cr_bitfield", crin_svdec),
1097                 (e.read_cr2, self.dec_cr_in, "cr_bitfield_b", crin_svdec_b),
1098                 (e.read_cr3, self.dec_cr_in, "cr_bitfield_o", crin_svdec_o),
1099                 (e.write_cr, self.dec_cr_out, "cr_bitfield", crout_svdec)):
1100                 fromreg = getattr(cr, name)
1101                 comb += svdec.extra.eq(extra)        # EXTRA field of SVP64 RM
1102                 comb += svdec.etype.eq(op.SV_Etype)  # EXTRA2/3 for this insn
1103                 comb += svdec.cr_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
1104                 with m.If(svdec.isvec):
1105                     # check if this is CR0 or CR1: treated differently
1106                     # (does not "listen" to EXTRA2/3 spec for a start)
1107                     # also: the CRs start from completely different locations
1108                     with m.If(cr.sv_override == 1): # CR0
1109                         offs = SVP64CROffs.CR0
1110                         comb += to_reg.data.eq(srcstep+offs)
1111                     with m.Elif(cr.sv_override == 2): # CR1
1112                         offs = SVP64CROffs.CR1
1113                         comb += to_reg.data.eq(srcstep+1)
1114                     with m.Else():
1115                         comb += to_reg.data.eq(srcstep+svdec.cr_out) # 7-bit out
1116                 with m.Else():
1117                     comb += to_reg.data.eq(svdec.cr_out) # 7-bit output
1118                 comb += to_reg.ok.eq(fromreg.ok)
1119
1120             # sigh must determine if RA is nonzero (7 bit)
1121             comb += self.sv_a_nz.eq(e.read_reg1.data != Const(0, 7))
1122         else:
1123             # connect up to/from read/write GPRs
1124             for to_reg, fromreg in ((e.read_reg1, dec_a.reg_out),
1125                                     (e.read_reg2, dec_b.reg_out),
1126                                     (e.read_reg3, dec_c.reg_out),
1127                                     (e.write_reg, dec_o.reg_out),
1128                                     (e.write_ea, dec_o2.reg_out)):
1129                 comb += to_reg.data.eq(fromreg.data)
1130                 comb += to_reg.ok.eq(fromreg.ok)
1131
1132             # connect up to/from read/write CRs
1133             for to_reg, cr, name in (
1134                         (e.read_cr1, self.dec_cr_in, "cr_bitfield", ),
1135                         (e.read_cr2, self.dec_cr_in, "cr_bitfield_b", ),
1136                         (e.read_cr3, self.dec_cr_in, "cr_bitfield_o", ),
1137                         (e.write_cr, self.dec_cr_out, "cr_bitfield", )):
1138                 fromreg = getattr(cr, name)
1139                 comb += to_reg.data.eq(fromreg.data)
1140                 comb += to_reg.ok.eq(fromreg.ok)
1141
1142         # SPRs out
1143         comb += e.read_spr1.eq(dec_a.spr_out)
1144         comb += e.write_spr.eq(dec_o.spr_out)
1145
1146         # Fast regs out
1147         comb += e.read_fast1.eq(dec_a.fast_out)
1148         comb += e.read_fast2.eq(dec_b.fast_out)
1149         comb += e.write_fast1.eq(dec_o.fast_out)
1150         comb += e.write_fast2.eq(dec_o2.fast_out)
1151
1152         # sigh this is exactly the sort of thing for which the
1153         # decoder is designed to not need.  MTSPR, MFSPR and others need
1154         # access to the XER bits.  however setting e.oe is not appropriate
1155         with m.If(op.internal_op == MicrOp.OP_MFSPR):
1156             comb += e.xer_in.eq(0b111) # SO, CA, OV
1157         with m.If(op.internal_op == MicrOp.OP_CMP):
1158             comb += e.xer_in.eq(1<<XERRegs.SO) # SO
1159         with m.If(op.internal_op == MicrOp.OP_MTSPR):
1160             comb += e.xer_out.eq(1)
1161
1162         # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1163         with m.If(op.internal_op == MicrOp.OP_TRAP):
1164             # *DO NOT* call self.trap here.  that would reset absolutely
1165             # everything including destroying read of RA and RB.
1166             comb += self.do_copy("trapaddr", 0x70) # strip first nibble
1167
1168         ####################
1169         # ok so the instruction's been decoded, blah blah, however
1170         # now we need to determine if it's actually going to go ahead...
1171         # *or* if in fact it's a privileged operation, whether there's
1172         # an external interrupt, etc. etc.  this is a simple priority
1173         # if-elif-elif sequence.  decrement takes highest priority,
1174         # EINT next highest, privileged operation third.
1175
1176         # check if instruction is privileged
1177         is_priv_insn = instr_is_priv(m, op.internal_op, e.do.insn)
1178
1179         # different IRQ conditions
1180         ext_irq_ok = Signal()
1181         dec_irq_ok = Signal()
1182         priv_ok = Signal()
1183         illeg_ok = Signal()
1184         exc = self.exc
1185
1186         comb += ext_irq_ok.eq(ext_irq & msr[MSR.EE]) # v3.0B p944 (MSR.EE)
1187         comb += dec_irq_ok.eq(dec_spr[63] & msr[MSR.EE]) # 6.5.11 p1076
1188         comb += priv_ok.eq(is_priv_insn & msr[MSR.PR])
1189         comb += illeg_ok.eq(op.internal_op == MicrOp.OP_ILLEGAL)
1190
1191         # LD/ST exceptions.  TestIssuer copies the exception info at us
1192         # after a failed LD/ST.
1193         with m.If(exc.happened):
1194             with m.If(exc.alignment):
1195                 self.trap(m, TT.PRIV, 0x600)
1196             with m.Elif(exc.instr_fault):
1197                 with m.If(exc.segment_fault):
1198                     self.trap(m, TT.PRIV, 0x480)
1199                 with m.Else():
1200                     # pass exception info to trap to create SRR1
1201                     self.trap(m, TT.MEMEXC, 0x400, exc)
1202             with m.Else():
1203                 with m.If(exc.segment_fault):
1204                     self.trap(m, TT.PRIV, 0x380)
1205                 with m.Else():
1206                     self.trap(m, TT.PRIV, 0x300)
1207
1208         # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1209         with m.Elif(dec_irq_ok):
1210             self.trap(m, TT.DEC, 0x900)   # v3.0B 6.5 p1065
1211
1212         # external interrupt? only if MSR.EE set
1213         with m.Elif(ext_irq_ok):
1214             self.trap(m, TT.EINT, 0x500)
1215
1216         # privileged instruction trap
1217         with m.Elif(priv_ok):
1218             self.trap(m, TT.PRIV, 0x700)
1219
1220         # illegal instruction must redirect to trap. this is done by
1221         # *overwriting* the decoded instruction and starting again.
1222         # (note: the same goes for interrupts and for privileged operations,
1223         # just with different trapaddr and traptype)
1224         with m.Elif(illeg_ok):
1225             # illegal instruction trap
1226             self.trap(m, TT.ILLEG, 0x700)
1227
1228         # no exception, just copy things to the output
1229         with m.Else():
1230             comb += e_out.eq(e)
1231
1232         ####################
1233         # follow-up after trap/irq to set up SRR0/1
1234
1235         # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1236         # Note: OP_SC could actually be modified to just be a trap
1237         with m.If((do_out.insn_type == MicrOp.OP_TRAP) |
1238                   (do_out.insn_type == MicrOp.OP_SC)):
1239             # TRAP write fast1 = SRR0
1240             comb += e_out.write_fast1.data.eq(FastRegs.SRR0)  # constant: SRR0
1241             comb += e_out.write_fast1.ok.eq(1)
1242             # TRAP write fast2 = SRR1
1243             comb += e_out.write_fast2.data.eq(FastRegs.SRR1)  # constant: SRR1
1244             comb += e_out.write_fast2.ok.eq(1)
1245
1246         # RFID: needs to read SRR0/1
1247         with m.If(do_out.insn_type == MicrOp.OP_RFID):
1248             # TRAP read fast1 = SRR0
1249             comb += e_out.read_fast1.data.eq(FastRegs.SRR0)  # constant: SRR0
1250             comb += e_out.read_fast1.ok.eq(1)
1251             # TRAP read fast2 = SRR1
1252             comb += e_out.read_fast2.data.eq(FastRegs.SRR1)  # constant: SRR1
1253             comb += e_out.read_fast2.ok.eq(1)
1254
1255         # annoying simulator bug
1256         if hasattr(e_out, "asmcode") and hasattr(self.dec.op, "asmcode"):
1257             comb += e_out.asmcode.eq(self.dec.op.asmcode)
1258
1259         return m
1260
1261     def trap(self, m, traptype, trapaddr, exc=None):
1262         """trap: this basically "rewrites" the decoded instruction as a trap
1263         """
1264         comb = m.d.comb
1265         op, e = self.dec.op, self.e
1266         comb += e.eq(0)  # reset eeeeeverything
1267
1268         # start again
1269         comb += self.do_copy("insn", self.dec.opcode_in, True)
1270         comb += self.do_copy("insn_type", MicrOp.OP_TRAP, True)
1271         comb += self.do_copy("fn_unit", Function.TRAP, True)
1272         comb += self.do_copy("trapaddr", trapaddr >> 4, True) # bottom 4 bits
1273         comb += self.do_copy("traptype", traptype, True)  # request type
1274         comb += self.do_copy("ldst_exc", exc, True)  # request type
1275         comb += self.do_copy("msr", self.state.msr, True) # copy of MSR "state"
1276         comb += self.do_copy("cia", self.state.pc, True)  # copy of PC "state"
1277
1278
1279
1280 def get_rdflags(e, cu):
1281     rdl = []
1282     for idx in range(cu.n_src):
1283         regfile, regname, _ = cu.get_in_spec(idx)
1284         rdflag, read = regspec_decode_read(e, regfile, regname)
1285         rdl.append(rdflag)
1286     print("rdflags", rdl)
1287     return Cat(*rdl)
1288
1289
1290 if __name__ == '__main__':
1291     pdecode = create_pdecode()
1292     dec2 = PowerDecode2(pdecode)
1293     vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
1294     with open("dec2.il", "w") as f:
1295         f.write(vl)