src/soc/decoder/power_decoder2.py

   1 """Power ISA Decoder second stage
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
   6 over-riding the internal opcode when an exception is needed.
   7 """
   8
   9 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
  10 from nmigen.cli import rtlil
  11 from soc.regfile.regfiles import XERRegs
  12
  13 from nmutil.picker import PriorityPicker
  14 from nmutil.iocontrol import RecordObject
  15 from nmutil.extend import exts
  16
  17 from soc.decoder.power_regspec_map import regspec_decode_read
  18 from soc.decoder.power_regspec_map import regspec_decode_write
  19 from soc.decoder.power_decoder import create_pdecode
  20 from soc.decoder.power_enums import (MicrOp, CryIn, Function,
  21                                      CRInSel, CROutSel,
  22                                      LdstLen, In1Sel, In2Sel, In3Sel,
  23                                      OutSel, SPR, RC, LDSTMode)
  24 from soc.decoder.decode2execute1 import Decode2ToExecute1Type, Data
  25 from soc.consts import MSR
  26
  27 from soc.regfile.regfiles import FastRegs
  28 from soc.consts import TT
  29 from soc.config.state import CoreState
  30
  31
  32 def decode_spr_num(spr):
  33     return Cat(spr[5:10], spr[0:5])
  34
  35
  36 def instr_is_priv(m, op, insn):
  37     """determines if the instruction is privileged or not
  38     """
  39     comb = m.d.comb
  40     is_priv_insn = Signal(reset_less=True)
  41     with m.Switch(op):
  42         with m.Case(MicrOp.OP_ATTN, MicrOp.OP_MFMSR, MicrOp.OP_MTMSRD,
  43                     MicrOp.OP_MTMSR, MicrOp.OP_RFID):
  44             comb += is_priv_insn.eq(1)
  45         # XXX TODO
  46         #with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
  47         with m.Case(MicrOp.OP_MFSPR, MicrOp.OP_MTSPR):
  48             with m.If(insn[20]):  # field XFX.spr[-1] i think
  49                 comb += is_priv_insn.eq(1)
  50     return is_priv_insn
  51
  52
  53 class SPRMap(Elaboratable):
  54     """SPRMap: maps POWER9 SPR numbers to internal enum values
  55     """
  56
  57     def __init__(self):
  58         self.spr_i = Signal(10, reset_less=True)
  59         self.spr_o = Signal(SPR, reset_less=True)
  60
  61     def elaborate(self, platform):
  62         m = Module()
  63         with m.Switch(self.spr_i):
  64             for i, x in enumerate(SPR):
  65                 with m.Case(x.value):
  66                     m.d.comb += self.spr_o.eq(i)
  67         return m
  68
  69
  70 class DecodeA(Elaboratable):
  71     """DecodeA from instruction
  72
  73     decodes register RA, whether immediate-zero, implicit and
  74     explicit CSRs
  75     """
  76
  77     def __init__(self, dec):
  78         self.dec = dec
  79         self.sel_in = Signal(In1Sel, reset_less=True)
  80         self.insn_in = Signal(32, reset_less=True)
  81         self.reg_out = Data(5, name="reg_a")
  82         self.immz_out = Signal(reset_less=True)
  83         self.spr_out = Data(SPR, "spr_a")
  84         self.fast_out = Data(3, "fast_a")
  85
  86     def elaborate(self, platform):
  87         m = Module()
  88         comb = m.d.comb
  89         m.submodules.sprmap = sprmap = SPRMap()
  90
  91         # select Register A field
  92         ra = Signal(5, reset_less=True)
  93         comb += ra.eq(self.dec.RA)
  94         with m.If((self.sel_in == In1Sel.RA) |
  95                   ((self.sel_in == In1Sel.RA_OR_ZERO) &
  96                    (ra != Const(0, 5)))):
  97             comb += self.reg_out.data.eq(ra)
  98             comb += self.reg_out.ok.eq(1)
  99
 100         # zero immediate requested
 101         with m.If((self.sel_in == In1Sel.RA_OR_ZERO) &
 102                   (self.reg_out.data == Const(0, 5))):
 103             comb += self.immz_out.eq(1)
 104
 105         # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
 106         with m.If(self.sel_in == In1Sel.RS):
 107             comb += self.reg_out.data.eq(self.dec.RS)
 108             comb += self.reg_out.ok.eq(1)
 109
 110         # decode Fast-SPR based on instruction type
 111         op = self.dec.op
 112         with m.Switch(op.internal_op):
 113
 114             # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
 115             with m.Case(MicrOp.OP_BC):
 116                 with m.If(~self.dec.BO[2]):  # 3.0B p38 BO2=0, use CTR reg
 117                     # constant: CTR
 118                     comb += self.fast_out.data.eq(FastRegs.CTR)
 119                     comb += self.fast_out.ok.eq(1)
 120             with m.Case(MicrOp.OP_BCREG):
 121                 xo9 = self.dec.FormXL.XO[9]  # 3.0B p38 top bit of XO
 122                 xo5 = self.dec.FormXL.XO[5]  # 3.0B p38
 123                 with m.If(xo9 & ~xo5):
 124                     # constant: CTR
 125                     comb += self.fast_out.data.eq(FastRegs.CTR)
 126                     comb += self.fast_out.ok.eq(1)
 127
 128             # MFSPR move from SPRs
 129             with m.Case(MicrOp.OP_MFSPR):
 130                 spr = Signal(10, reset_less=True)
 131                 comb += spr.eq(decode_spr_num(self.dec.SPR))  # from XFX
 132                 with m.Switch(spr):
 133                     # fast SPRs
 134                     with m.Case(SPR.CTR.value):
 135                         comb += self.fast_out.data.eq(FastRegs.CTR)
 136                         comb += self.fast_out.ok.eq(1)
 137                     with m.Case(SPR.LR.value):
 138                         comb += self.fast_out.data.eq(FastRegs.LR)
 139                         comb += self.fast_out.ok.eq(1)
 140                     with m.Case(SPR.TAR.value):
 141                         comb += self.fast_out.data.eq(FastRegs.TAR)
 142                         comb += self.fast_out.ok.eq(1)
 143                     with m.Case(SPR.SRR0.value):
 144                         comb += self.fast_out.data.eq(FastRegs.SRR0)
 145                         comb += self.fast_out.ok.eq(1)
 146                     with m.Case(SPR.SRR1.value):
 147                         comb += self.fast_out.data.eq(FastRegs.SRR1)
 148                         comb += self.fast_out.ok.eq(1)
 149                     with m.Case(SPR.XER.value):
 150                         comb += self.fast_out.data.eq(FastRegs.XER)
 151                         comb += self.fast_out.ok.eq(1)
 152                     with m.Case(SPR.DEC.value):
 153                         comb += self.fast_out.data.eq(FastRegs.DEC)
 154                         comb += self.fast_out.ok.eq(1)
 155                     with m.Case(SPR.TB.value):
 156                         comb += self.fast_out.data.eq(FastRegs.TB)
 157                         comb += self.fast_out.ok.eq(1)
 158                     # : map to internal SPR numbers
 159                     # XXX TODO: dec and tb not to go through mapping.
 160                     with m.Default():
 161                         comb += sprmap.spr_i.eq(spr)
 162                         comb += self.spr_out.data.eq(sprmap.spr_o)
 163                         comb += self.spr_out.ok.eq(1)
 164
 165         return m
 166
 167
 168 class DecodeB(Elaboratable):
 169     """DecodeB from instruction
 170
 171     decodes register RB, different forms of immediate (signed, unsigned),
 172     and implicit SPRs.  register B is basically "lane 2" into the CompUnits.
 173     by industry-standard convention, "lane 2" is where fully-decoded
 174     immediates are muxed in.
 175     """
 176
 177     def __init__(self, dec):
 178         self.dec = dec
 179         self.sel_in = Signal(In2Sel, reset_less=True)
 180         self.insn_in = Signal(32, reset_less=True)
 181         self.reg_out = Data(5, "reg_b")
 182         self.imm_out = Data(64, "imm_b")
 183         self.fast_out = Data(3, "fast_b")
 184
 185     def elaborate(self, platform):
 186         m = Module()
 187         comb = m.d.comb
 188
 189         # select Register B field
 190         with m.Switch(self.sel_in):
 191             with m.Case(In2Sel.RB):
 192                 comb += self.reg_out.data.eq(self.dec.RB)
 193                 comb += self.reg_out.ok.eq(1)
 194             with m.Case(In2Sel.RS):
 195                 # for M-Form shiftrot
 196                 comb += self.reg_out.data.eq(self.dec.RS)
 197                 comb += self.reg_out.ok.eq(1)
 198             with m.Case(In2Sel.CONST_UI): # unsigned
 199                 comb += self.imm_out.data.eq(self.dec.UI)
 200                 comb += self.imm_out.ok.eq(1)
 201             with m.Case(In2Sel.CONST_SI):  # sign-extended 16-bit
 202                 si = Signal(16, reset_less=True)
 203                 comb += si.eq(self.dec.SI)
 204                 comb += self.imm_out.data.eq(exts(si, 16, 64))
 205                 comb += self.imm_out.ok.eq(1)
 206             with m.Case(In2Sel.CONST_SI_HI):  # sign-extended 16+16=32 bit
 207                 si_hi = Signal(32, reset_less=True)
 208                 comb += si_hi.eq(self.dec.SI << 16)
 209                 comb += self.imm_out.data.eq(exts(si_hi, 32, 64))
 210                 comb += self.imm_out.ok.eq(1)
 211             with m.Case(In2Sel.CONST_UI_HI): # unsigned
 212                 ui = Signal(16, reset_less=True)
 213                 comb += ui.eq(self.dec.UI)
 214                 comb += self.imm_out.data.eq(ui << 16)
 215                 comb += self.imm_out.ok.eq(1)
 216             with m.Case(In2Sel.CONST_LI): # sign-extend 24+2=26 bit
 217                 li = Signal(26, reset_less=True)
 218                 comb += li.eq(self.dec.LI << 2)
 219                 comb += self.imm_out.data.eq(exts(li, 26, 64))
 220                 comb += self.imm_out.ok.eq(1)
 221             with m.Case(In2Sel.CONST_BD): # sign-extend (14+2)=16 bit
 222                 bd = Signal(16, reset_less=True)
 223                 comb += bd.eq(self.dec.BD << 2)
 224                 comb += self.imm_out.data.eq(exts(bd, 16, 64))
 225                 comb += self.imm_out.ok.eq(1)
 226             with m.Case(In2Sel.CONST_DS): # sign-extended (14+2=16) bit
 227                 ds = Signal(16, reset_less=True)
 228                 comb += ds.eq(self.dec.DS << 2)
 229                 comb += self.imm_out.data.eq(exts(ds, 16, 64))
 230                 comb += self.imm_out.ok.eq(1)
 231             with m.Case(In2Sel.CONST_M1): # signed (-1)
 232                 comb += self.imm_out.data.eq(~Const(0, 64))  # all 1s
 233                 comb += self.imm_out.ok.eq(1)
 234             with m.Case(In2Sel.CONST_SH): # unsigned - for shift
 235                 comb += self.imm_out.data.eq(self.dec.sh)
 236                 comb += self.imm_out.ok.eq(1)
 237             with m.Case(In2Sel.CONST_SH32): # unsigned - for shift
 238                 comb += self.imm_out.data.eq(self.dec.SH32)
 239                 comb += self.imm_out.ok.eq(1)
 240
 241         # decode SPR2 based on instruction type
 242         op = self.dec.op
 243         # BCREG implicitly uses LR or TAR for 2nd reg
 244         # CTR however is already in fast_spr1 *not* 2.
 245         with m.If(op.internal_op == MicrOp.OP_BCREG):
 246             xo9 = self.dec.FormXL.XO[9]  # 3.0B p38 top bit of XO
 247             xo5 = self.dec.FormXL.XO[5]  # 3.0B p38
 248             with m.If(~xo9):
 249                 comb += self.fast_out.data.eq(FastRegs.LR)
 250                 comb += self.fast_out.ok.eq(1)
 251             with m.Elif(xo5):
 252                 comb += self.fast_out.data.eq(FastRegs.TAR)
 253                 comb += self.fast_out.ok.eq(1)
 254
 255         return m
 256
 257
 258 class DecodeC(Elaboratable):
 259     """DecodeC from instruction
 260
 261     decodes register RC.  this is "lane 3" into some CompUnits (not many)
 262     """
 263
 264     def __init__(self, dec):
 265         self.dec = dec
 266         self.sel_in = Signal(In3Sel, reset_less=True)
 267         self.insn_in = Signal(32, reset_less=True)
 268         self.reg_out = Data(5, "reg_c")
 269
 270     def elaborate(self, platform):
 271         m = Module()
 272         comb = m.d.comb
 273
 274         # select Register C field
 275         with m.Switch(self.sel_in):
 276             with m.Case(In3Sel.RB):
 277                 # for M-Form shiftrot
 278                 comb += self.reg_out.data.eq(self.dec.RB)
 279                 comb += self.reg_out.ok.eq(1)
 280             with m.Case(In3Sel.RS):
 281                 comb += self.reg_out.data.eq(self.dec.RS)
 282                 comb += self.reg_out.ok.eq(1)
 283
 284         return m
 285
 286
 287 class DecodeOut(Elaboratable):
 288     """DecodeOut from instruction
 289
 290     decodes output register RA, RT or SPR
 291     """
 292
 293     def __init__(self, dec):
 294         self.dec = dec
 295         self.sel_in = Signal(OutSel, reset_less=True)
 296         self.insn_in = Signal(32, reset_less=True)
 297         self.reg_out = Data(5, "reg_o")
 298         self.spr_out = Data(SPR, "spr_o")
 299         self.fast_out = Data(3, "fast_o")
 300
 301     def elaborate(self, platform):
 302         m = Module()
 303         comb = m.d.comb
 304         m.submodules.sprmap = sprmap = SPRMap()
 305         op = self.dec.op
 306
 307         # select Register out field
 308         with m.Switch(self.sel_in):
 309             with m.Case(OutSel.RT):
 310                 comb += self.reg_out.data.eq(self.dec.RT)
 311                 comb += self.reg_out.ok.eq(1)
 312             with m.Case(OutSel.RA):
 313                 comb += self.reg_out.data.eq(self.dec.RA)
 314                 comb += self.reg_out.ok.eq(1)
 315             with m.Case(OutSel.SPR):
 316                 spr = Signal(10, reset_less=True)
 317                 comb += spr.eq(decode_spr_num(self.dec.SPR))  # from XFX
 318                 # TODO MTSPR 1st spr (fast)
 319                 with m.If(op.internal_op == MicrOp.OP_MTSPR):
 320                     with m.Switch(spr):
 321                         # fast SPRs
 322                         with m.Case(SPR.CTR.value):
 323                             comb += self.fast_out.data.eq(FastRegs.CTR)
 324                             comb += self.fast_out.ok.eq(1)
 325                         with m.Case(SPR.LR.value):
 326                             comb += self.fast_out.data.eq(FastRegs.LR)
 327                             comb += self.fast_out.ok.eq(1)
 328                         with m.Case(SPR.TAR.value):
 329                             comb += self.fast_out.data.eq(FastRegs.TAR)
 330                             comb += self.fast_out.ok.eq(1)
 331                         with m.Case(SPR.SRR0.value):
 332                             comb += self.fast_out.data.eq(FastRegs.SRR0)
 333                             comb += self.fast_out.ok.eq(1)
 334                         with m.Case(SPR.SRR1.value):
 335                             comb += self.fast_out.data.eq(FastRegs.SRR1)
 336                             comb += self.fast_out.ok.eq(1)
 337                         with m.Case(SPR.XER.value):
 338                             comb += self.fast_out.data.eq(FastRegs.XER)
 339                             comb += self.fast_out.ok.eq(1)
 340                         with m.Case(SPR.TB.value):
 341                             comb += self.fast_out.data.eq(FastRegs.TB)
 342                             comb += self.fast_out.ok.eq(1)
 343                         with m.Case(SPR.DEC.value):
 344                             comb += self.fast_out.data.eq(FastRegs.DEC)
 345                             comb += self.fast_out.ok.eq(1)
 346                         # : map to internal SPR numbers
 347                         # XXX TODO: dec and tb not to go through mapping.
 348                         with m.Default():
 349                             comb += sprmap.spr_i.eq(spr)
 350                             comb += self.spr_out.data.eq(sprmap.spr_o)
 351                             comb += self.spr_out.ok.eq(1)
 352
 353         with m.Switch(op.internal_op):
 354
 355             # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
 356             with m.Case(MicrOp.OP_BC, MicrOp.OP_BCREG):
 357                 with m.If(~self.dec.BO[2]):  # 3.0B p38 BO2=0, use CTR reg
 358                     # constant: CTR
 359                     comb += self.fast_out.data.eq(FastRegs.CTR)
 360                     comb += self.fast_out.ok.eq(1)
 361
 362             # RFID 1st spr (fast)
 363             with m.Case(MicrOp.OP_RFID):
 364                 comb += self.fast_out.data.eq(FastRegs.SRR0)  # constant: SRR0
 365                 comb += self.fast_out.ok.eq(1)
 366
 367         return m
 368
 369
 370 class DecodeOut2(Elaboratable):
 371     """DecodeOut2 from instruction
 372
 373     decodes output registers
 374     """
 375
 376     def __init__(self, dec):
 377         self.dec = dec
 378         self.sel_in = Signal(OutSel, reset_less=True)
 379         self.lk = Signal(reset_less=True)
 380         self.insn_in = Signal(32, reset_less=True)
 381         self.reg_out = Data(5, "reg_o")
 382         self.fast_out = Data(3, "fast_o")
 383
 384     def elaborate(self, platform):
 385         m = Module()
 386         comb = m.d.comb
 387
 388         # update mode LD/ST uses read-reg A also as an output
 389         with m.If(self.dec.op.upd == LDSTMode.update):
 390             comb += self.reg_out.eq(self.dec.RA)
 391             comb += self.reg_out.ok.eq(1)
 392
 393         # B, BC or BCREG: potential implicit register (LR) output
 394         # these give bl, bcl, bclrl, etc.
 395         op = self.dec.op
 396         with m.Switch(op.internal_op):
 397
 398             # BC* implicit register (LR)
 399             with m.Case(MicrOp.OP_BC, MicrOp.OP_B, MicrOp.OP_BCREG):
 400                 with m.If(self.lk):  # "link" mode
 401                     comb += self.fast_out.data.eq(FastRegs.LR)  # constant: LR
 402                     comb += self.fast_out.ok.eq(1)
 403
 404             # RFID 2nd spr (fast)
 405             with m.Case(MicrOp.OP_RFID):
 406                 comb += self.fast_out.data.eq(FastRegs.SRR1)  # constant: SRR1
 407                 comb += self.fast_out.ok.eq(1)
 408
 409         return m
 410
 411
 412 class DecodeRC(Elaboratable):
 413     """DecodeRc from instruction
 414
 415     decodes Record bit Rc
 416     """
 417
 418     def __init__(self, dec):
 419         self.dec = dec
 420         self.sel_in = Signal(RC, reset_less=True)
 421         self.insn_in = Signal(32, reset_less=True)
 422         self.rc_out = Data(1, "rc")
 423
 424     def elaborate(self, platform):
 425         m = Module()
 426         comb = m.d.comb
 427
 428         # select Record bit out field
 429         with m.Switch(self.sel_in):
 430             with m.Case(RC.RC):
 431                 comb += self.rc_out.data.eq(self.dec.Rc)
 432                 comb += self.rc_out.ok.eq(1)
 433             with m.Case(RC.ONE):
 434                 comb += self.rc_out.data.eq(1)
 435                 comb += self.rc_out.ok.eq(1)
 436             with m.Case(RC.NONE):
 437                 comb += self.rc_out.data.eq(0)
 438                 comb += self.rc_out.ok.eq(1)
 439
 440         return m
 441
 442
 443 class DecodeOE(Elaboratable):
 444     """DecodeOE from instruction
 445
 446     decodes OE field: uses RC decode detection which might not be good
 447
 448     -- For now, use "rc" in the decode table to decide whether oe exists.
 449     -- This is not entirely correct architecturally: For mulhd and
 450     -- mulhdu, the OE field is reserved. It remains to be seen what an
 451     -- actual POWER9 does if we set it on those instructions, for now we
 452     -- test that further down when assigning to the multiplier oe input.
 453     """
 454
 455     def __init__(self, dec):
 456         self.dec = dec
 457         self.sel_in = Signal(RC, reset_less=True)
 458         self.insn_in = Signal(32, reset_less=True)
 459         self.oe_out = Data(1, "oe")
 460
 461     def elaborate(self, platform):
 462         m = Module()
 463         comb = m.d.comb
 464         op = self.dec.op
 465
 466         with m.Switch(op.internal_op):
 467
 468             # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
 469             # also rotate
 470             # XXX ARGH! ignoring OE causes incompatibility with microwatt
 471             # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
 472             with m.Case(MicrOp.OP_MUL_H64, MicrOp.OP_MUL_H32,
 473                         MicrOp.OP_EXTS, MicrOp.OP_CNTZ,
 474                         MicrOp.OP_SHL, MicrOp.OP_SHR, MicrOp.OP_RLC,
 475                         MicrOp.OP_LOAD, MicrOp.OP_STORE,
 476                         MicrOp.OP_RLCL, MicrOp.OP_RLCR,
 477                         MicrOp.OP_EXTSWSLI):
 478                 pass
 479
 480             # all other ops decode OE field
 481             with m.Default():
 482                 # select OE bit out field
 483                 with m.Switch(self.sel_in):
 484                     with m.Case(RC.RC):
 485                         comb += self.oe_out.data.eq(self.dec.OE)
 486                         comb += self.oe_out.ok.eq(1)
 487
 488         return m
 489
 490
 491 class DecodeCRIn(Elaboratable):
 492     """Decodes input CR from instruction
 493
 494     CR indices - insn fields - (not the data *in* the CR) require only 3
 495     bits because they refer to CR0-CR7
 496     """
 497
 498     def __init__(self, dec):
 499         self.dec = dec
 500         self.sel_in = Signal(CRInSel, reset_less=True)
 501         self.insn_in = Signal(32, reset_less=True)
 502         self.cr_bitfield = Data(3, "cr_bitfield")
 503         self.cr_bitfield_b = Data(3, "cr_bitfield_b")
 504         self.cr_bitfield_o = Data(3, "cr_bitfield_o")
 505         self.whole_reg = Data(8,  "cr_fxm")
 506
 507     def elaborate(self, platform):
 508         m = Module()
 509         m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
 510                                                        reverse_o=True)
 511
 512         comb = m.d.comb
 513         op = self.dec.op
 514
 515         comb += self.cr_bitfield.ok.eq(0)
 516         comb += self.cr_bitfield_b.ok.eq(0)
 517         comb += self.whole_reg.ok.eq(0)
 518         with m.Switch(self.sel_in):
 519             with m.Case(CRInSel.NONE):
 520                 pass  # No bitfield activated
 521             with m.Case(CRInSel.CR0):
 522                 comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering)
 523                 comb += self.cr_bitfield.ok.eq(1)
 524             with m.Case(CRInSel.BI):
 525                 comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
 526                 comb += self.cr_bitfield.ok.eq(1)
 527             with m.Case(CRInSel.BFA):
 528                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
 529                 comb += self.cr_bitfield.ok.eq(1)
 530             with m.Case(CRInSel.BA_BB):
 531                 comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
 532                 comb += self.cr_bitfield.ok.eq(1)
 533                 comb += self.cr_bitfield_b.data.eq(self.dec.BB[2:5])
 534                 comb += self.cr_bitfield_b.ok.eq(1)
 535                 comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
 536                 comb += self.cr_bitfield_o.ok.eq(1)
 537             with m.Case(CRInSel.BC):
 538                 comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
 539                 comb += self.cr_bitfield.ok.eq(1)
 540             with m.Case(CRInSel.WHOLE_REG):
 541                 comb += self.whole_reg.ok.eq(1)
 542                 move_one = Signal(reset_less=True)
 543                 comb += move_one.eq(self.insn_in[20]) # MSB0 bit 11
 544                 with m.If((op.internal_op == MicrOp.OP_MFCR) & move_one):
 545                     # must one-hot the FXM field
 546                     comb += ppick.i.eq(self.dec.FXM)
 547                     comb += self.whole_reg.data.eq(ppick.o)
 548                 with m.Else():
 549                     # otherwise use all of it
 550                     comb += self.whole_reg.data.eq(0xff)
 551
 552         return m
 553
 554
 555 class DecodeCROut(Elaboratable):
 556     """Decodes input CR from instruction
 557
 558     CR indices - insn fields - (not the data *in* the CR) require only 3
 559     bits because they refer to CR0-CR7
 560     """
 561
 562     def __init__(self, dec):
 563         self.dec = dec
 564         self.rc_in = Signal(reset_less=True)
 565         self.sel_in = Signal(CROutSel, reset_less=True)
 566         self.insn_in = Signal(32, reset_less=True)
 567         self.cr_bitfield = Data(3, "cr_bitfield")
 568         self.whole_reg = Data(8,  "cr_fxm")
 569
 570     def elaborate(self, platform):
 571         m = Module()
 572         comb = m.d.comb
 573         op = self.dec.op
 574         m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
 575                                                        reverse_o=True)
 576
 577         comb += self.cr_bitfield.ok.eq(0)
 578         comb += self.whole_reg.ok.eq(0)
 579         with m.Switch(self.sel_in):
 580             with m.Case(CROutSel.NONE):
 581                 pass  # No bitfield activated
 582             with m.Case(CROutSel.CR0):
 583                 comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering)
 584                 comb += self.cr_bitfield.ok.eq(self.rc_in)  # only when RC=1
 585             with m.Case(CROutSel.BF):
 586                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BF)
 587                 comb += self.cr_bitfield.ok.eq(1)
 588             with m.Case(CROutSel.BT):
 589                 comb += self.cr_bitfield.data.eq(self.dec.FormXL.BT[2:5])
 590                 comb += self.cr_bitfield.ok.eq(1)
 591             with m.Case(CROutSel.WHOLE_REG):
 592                 comb += self.whole_reg.ok.eq(1)
 593                 move_one = Signal(reset_less=True)
 594                 comb += move_one.eq(self.insn_in[20])
 595                 with m.If((op.internal_op == MicrOp.OP_MTCRF)):
 596                     with m.If(move_one):
 597                         # must one-hot the FXM field
 598                         comb += ppick.i.eq(self.dec.FXM)
 599                         with m.If(ppick.en_o):
 600                             comb += self.whole_reg.data.eq(ppick.o)
 601                         with m.Else():
 602                             comb += self.whole_reg.data.eq(0b00000001) # CR7
 603                     with m.Else():
 604                         comb += self.whole_reg.data.eq(self.dec.FXM)
 605                 with m.Else():
 606                     # otherwise use all of it
 607                     comb += self.whole_reg.data.eq(0xff)
 608
 609         return m
 610
 611
 612 class PowerDecode2(Elaboratable):
 613     """PowerDecode2: the main instruction decoder.
 614
 615     whilst PowerDecode is responsible for decoding the actual opcode, this
 616     module encapsulates further specialist, sparse information and
 617     expansion of fields that is inconvenient to have in the CSV files.
 618     for example: the encoding of the immediates, which are detected
 619     and expanded out to their full value from an annotated (enum)
 620     representation.
 621
 622     implicit register usage is also set up, here.  for example: OP_BC
 623     requires implicitly reading CTR, OP_RFID requires implicitly writing
 624     to SRR1 and so on.
 625
 626     in addition, PowerDecoder2 is responsible for detecting whether
 627     instructions are illegal (or privileged) or not, and instead of
 628     just leaving at that, *replacing* the instruction to execute with
 629     a suitable alternative (trap).
 630     """
 631
 632     def __init__(self, dec):
 633
 634         self.dec = dec
 635         self.e = Decode2ToExecute1Type()
 636
 637         # state information needed by the Decoder (TODO: this as a Record)
 638         self.state = CoreState("dec2")
 639
 640     def ports(self):
 641         return self.dec.ports() + self.e.ports()
 642
 643     def elaborate(self, platform):
 644         m = Module()
 645         comb = m.d.comb
 646         state = self.state
 647         e_out, op, do_out = self.e, self.dec.op, self.e.do
 648         dec_spr, msr, cia, ext_irq = state.dec, state.msr, state.pc, state.eint
 649
 650         # fill in for a normal instruction (not an exception)
 651         # copy over if non-exception, non-privileged etc. is detected
 652         e = Decode2ToExecute1Type()
 653         do = e.do
 654
 655         # set up submodule decoders
 656         m.submodules.dec = self.dec
 657         m.submodules.dec_a = dec_a = DecodeA(self.dec)
 658         m.submodules.dec_b = dec_b = DecodeB(self.dec)
 659         m.submodules.dec_c = dec_c = DecodeC(self.dec)
 660         m.submodules.dec_o = dec_o = DecodeOut(self.dec)
 661         m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
 662         m.submodules.dec_rc = dec_rc = DecodeRC(self.dec)
 663         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
 664         m.submodules.dec_cr_in = dec_cr_in = DecodeCRIn(self.dec)
 665         m.submodules.dec_cr_out = dec_cr_out = DecodeCROut(self.dec)
 666
 667         # copy instruction through...
 668         for i in [do.insn, dec_a.insn_in, dec_b.insn_in,
 669                   dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in, dec_rc.insn_in,
 670                   dec_oe.insn_in, dec_cr_in.insn_in, dec_cr_out.insn_in]:
 671             comb += i.eq(self.dec.opcode_in)
 672
 673         # ...and subdecoders' input fields
 674         comb += dec_a.sel_in.eq(op.in1_sel)
 675         comb += dec_b.sel_in.eq(op.in2_sel)
 676         comb += dec_c.sel_in.eq(op.in3_sel)
 677         comb += dec_o.sel_in.eq(op.out_sel)
 678         comb += dec_o2.sel_in.eq(op.out_sel)
 679         comb += dec_o2.lk.eq(do.lk)
 680         comb += dec_rc.sel_in.eq(op.rc_sel)
 681         comb += dec_oe.sel_in.eq(op.rc_sel)  # XXX should be OE sel
 682         comb += dec_cr_in.sel_in.eq(op.cr_in)
 683         comb += dec_cr_out.sel_in.eq(op.cr_out)
 684         comb += dec_cr_out.rc_in.eq(dec_rc.rc_out.data)
 685
 686         # copy "state" over
 687         comb += do.msr.eq(msr)
 688         comb += do.cia.eq(cia)
 689
 690         # set up instruction, pick fn unit
 691         # no op: defaults to OP_ILLEGAL
 692         comb += do.insn_type.eq(op.internal_op)
 693         comb += do.fn_unit.eq(op.function_unit)
 694
 695         # registers a, b, c and out and out2 (LD/ST EA)
 696         comb += e.read_reg1.eq(dec_a.reg_out)
 697         comb += e.read_reg2.eq(dec_b.reg_out)
 698         comb += e.read_reg3.eq(dec_c.reg_out)
 699         comb += e.write_reg.eq(dec_o.reg_out)
 700         comb += e.write_ea.eq(dec_o2.reg_out)
 701         comb += do.imm_data.eq(dec_b.imm_out)  # immediate in RB (usually)
 702         comb += do.zero_a.eq(dec_a.immz_out)  # RA==0 detected
 703
 704         # rc and oe out
 705         comb += do.rc.eq(dec_rc.rc_out)
 706         comb += do.oe.eq(dec_oe.oe_out)
 707
 708         # SPRs out
 709         comb += e.read_spr1.eq(dec_a.spr_out)
 710         comb += e.write_spr.eq(dec_o.spr_out)
 711
 712         # Fast regs out
 713         comb += e.read_fast1.eq(dec_a.fast_out)
 714         comb += e.read_fast2.eq(dec_b.fast_out)
 715         comb += e.write_fast1.eq(dec_o.fast_out)
 716         comb += e.write_fast2.eq(dec_o2.fast_out)
 717
 718         # condition registers (CR)
 719         comb += e.read_cr1.eq(dec_cr_in.cr_bitfield)
 720         comb += e.read_cr2.eq(dec_cr_in.cr_bitfield_b)
 721         comb += e.read_cr3.eq(dec_cr_in.cr_bitfield_o)
 722         comb += e.write_cr.eq(dec_cr_out.cr_bitfield)
 723
 724         comb += do.read_cr_whole.eq(dec_cr_in.whole_reg)
 725         comb += do.write_cr_whole.eq(dec_cr_out.whole_reg)
 726         comb += do.write_cr0.eq(dec_cr_out.cr_bitfield.ok)
 727
 728         # decoded/selected instruction flags
 729         comb += do.data_len.eq(op.ldst_len)
 730         comb += do.invert_in.eq(op.inv_a)
 731         comb += do.invert_out.eq(op.inv_out)
 732         comb += do.input_carry.eq(op.cry_in)   # carry comes in
 733         comb += do.output_carry.eq(op.cry_out)  # carry goes out
 734         comb += do.is_32bit.eq(op.is_32b)
 735         comb += do.is_signed.eq(op.sgn)
 736         with m.If(op.lk):
 737             comb += do.lk.eq(self.dec.LK)  # XXX TODO: accessor
 738
 739         comb += do.byte_reverse.eq(op.br)
 740         comb += do.sign_extend.eq(op.sgn_ext)
 741         comb += do.ldst_mode.eq(op.upd)  # LD/ST mode (update, cache-inhibit)
 742
 743         # These should be removed eventually
 744         comb += do.input_cr.eq(op.cr_in)   # condition reg comes in
 745         comb += do.output_cr.eq(op.cr_out)  # condition reg goes in
 746
 747         # sigh this is exactly the sort of thing for which the
 748         # decoder is designed to not need.  MTSPR, MFSPR and others need
 749         # access to the XER bits.  however setting e.oe is not appropriate
 750         with m.If(op.internal_op == MicrOp.OP_MFSPR):
 751             comb += e.xer_in.eq(0b111) # SO, CA, OV
 752         with m.If(op.internal_op == MicrOp.OP_CMP):
 753             comb += e.xer_in.eq(1<<XERRegs.SO) # SO
 754         with m.If(op.internal_op == MicrOp.OP_MTSPR):
 755             comb += e.xer_out.eq(1)
 756
 757         # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
 758         with m.If(op.internal_op == MicrOp.OP_TRAP):
 759             # *DO NOT* call self.trap here.  that would reset absolutely
 760             # rverything including destroying read of RA and RB.
 761             comb += do.trapaddr.eq(0x70)    # addr=0x700 (strip first nibble)
 762
 763         # check if instruction is privileged
 764         is_priv_insn = instr_is_priv(m, op.internal_op, e.do.insn)
 765
 766         # external interrupt? only if MSR.EE set
 767         with m.If(ext_irq & msr[MSR.EE]): # v3.0B p944 (MSR.EE)
 768             self.trap(m, TT.EINT, 0x500)
 769
 770         # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
 771         with m.If(dec_spr[63] & msr[MSR.EE]): # v3.0B 6.5.11 p1076
 772             self.trap(m, TT.DEC, 0x900)   # v3.0B 6.5 p1065
 773
 774         # privileged instruction trap
 775         with m.Elif(is_priv_insn & msr[MSR.PR]):
 776             self.trap(m, TT.PRIV, 0x700)
 777
 778         # illegal instruction must redirect to trap. this is done by
 779         # *overwriting* the decoded instruction and starting again.
 780         # (note: the same goes for interrupts and for privileged operations,
 781         # just with different trapaddr and traptype)
 782         with m.Elif(op.internal_op == MicrOp.OP_ILLEGAL):
 783             # illegal instruction trap
 784             self.trap(m, TT.ILLEG, 0x700)
 785
 786         # no exception, just copy things to the output
 787         with m.Else():
 788             comb += e_out.eq(e)
 789
 790         # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
 791         # Note: OP_SC could actually be modified to just be a trap
 792         with m.If((do_out.insn_type == MicrOp.OP_TRAP) |
 793                   (do_out.insn_type == MicrOp.OP_SC)):
 794             # TRAP write fast1 = SRR0
 795             comb += e_out.write_fast1.data.eq(FastRegs.SRR0)  # constant: SRR0
 796             comb += e_out.write_fast1.ok.eq(1)
 797             # TRAP write fast2 = SRR1
 798             comb += e_out.write_fast2.data.eq(FastRegs.SRR1)  # constant: SRR1
 799             comb += e_out.write_fast2.ok.eq(1)
 800
 801         # RFID: needs to read SRR0/1
 802         with m.If(do_out.insn_type == MicrOp.OP_RFID):
 803             # TRAP read fast1 = SRR0
 804             comb += e_out.read_fast1.data.eq(FastRegs.SRR0)  # constant: SRR0
 805             comb += e_out.read_fast1.ok.eq(1)
 806             # TRAP read fast2 = SRR1
 807             comb += e_out.read_fast2.data.eq(FastRegs.SRR1)  # constant: SRR1
 808             comb += e_out.read_fast2.ok.eq(1)
 809
 810         return m
 811
 812     def trap(self, m, traptype, trapaddr):
 813         """trap: this basically "rewrites" the decoded instruction as a trap
 814         """
 815         comb = m.d.comb
 816         op, do, e = self.dec.op, self.e.do, self.e
 817         comb += e.eq(0)  # reset eeeeeverything
 818
 819         # start again
 820         comb += do.insn.eq(self.dec.opcode_in)
 821         comb += do.insn_type.eq(MicrOp.OP_TRAP)
 822         comb += do.fn_unit.eq(Function.TRAP)
 823         comb += do.trapaddr.eq(trapaddr >> 4)  # cut bottom 4 bits
 824         comb += do.traptype.eq(traptype)  # request type
 825         comb += do.msr.eq(self.state.msr)  # copy of MSR "state"
 826         comb += do.cia.eq(self.state.pc)  # copy of PC "state"
 827
 828
 829 def get_rdflags(e, cu):
 830     rdl = []
 831     for idx in range(cu.n_src):
 832         regfile, regname, _ = cu.get_in_spec(idx)
 833         rdflag, read = regspec_decode_read(e, regfile, regname)
 834         rdl.append(rdflag)
 835     print("rdflags", rdl)
 836     return Cat(*rdl)
 837
 838
 839 if __name__ == '__main__':
 840     pdecode = create_pdecode()
 841     dec2 = PowerDecode2(pdecode)
 842     vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
 843     with open("dec2.il", "w") as f:
 844         f.write(vl)