src/soc/litex/florent/libresoc/core.py

   1 import os
   2
   3 from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
   4
   5 from litex.soc.interconnect import wishbone as wb
   6 from litex.soc.cores.cpu import CPU
   7
   8 from soc.config.pinouts import get_pinspecs
   9 from soc.debug.jtag import Pins
  10 from c4m.nmigen.jtag.tap import IOType
  11
  12 from libresoc.ls180 import io
  13 from litex.build.generic_platform import ConstraintManager
  14
  15
  16 CPU_VARIANTS = ["standard", "standard32", "standardjtag",
  17                 "standardjtagtestgpio", "ls180",
  18                 "standardjtagnoirq"]
  19
  20
  21 def make_wb_bus(prefix, obj, simple=False):
  22     res = {}
  23     outpins = ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel']
  24     if not simple:
  25         outpins += ['cti', 'bte']
  26     for o in outpins:
  27         res['o_%s__%s' % (prefix, o)] = getattr(obj, o)
  28     for i in ['ack', 'err', 'dat_r']:
  29         res['i_%s__%s' % (prefix, i)] = getattr(obj, i)
  30     return res
  31
  32 def make_wb_slave(prefix, obj, simple=False):
  33     res = {}
  34     inpins = ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel']
  35     if not simple:
  36         inpins += ['cti', 'bte']
  37     for i in inpins:
  38         res['i_%s__%s' % (prefix, i)] = getattr(obj, i)
  39     for o in ['ack', 'err', 'dat_r']:
  40         res['o_%s__%s' % (prefix, o)] = getattr(obj, o)
  41     return res
  42
  43 def make_pad(res, dirn, name, suffix, cpup, iop):
  44     cpud, iod = ('i', 'o') if dirn else ('o', 'i')
  45     cname = '%s_%s__core__%s' % (cpud, name, suffix)
  46     pname = '%s_%s__pad__%s' % (iod, name, suffix)
  47     print ("make pad", name, dirn, cpud, iod, cname, pname, suffix, cpup, iop)
  48     res[cname], res[pname] = cpup, iop
  49
  50 def get_field(rec, name):
  51     for f in rec.layout:
  52         f = f[0]
  53         if f.endswith(name):
  54             return getattr(rec, f)
  55
  56
  57 def make_jtag_ioconn(res, pin, cpupads, iopads):
  58     (fn, pin, iotype, pin_name, scan_idx) = pin
  59     #serial_tx__core__o, serial_rx__pad__i,
  60     # special-case sdram_clock
  61     if pin == 'clock' and fn == 'sdr':
  62         cpu = cpupads['sdram_clock']
  63         io = iopads['sdram_clock']
  64     else:
  65         cpu = cpupads[fn]
  66         io = iopads[fn]
  67     print ("cpupads", cpupads)
  68     print ("iopads", iopads)
  69     print ("pin", fn, pin, iotype, pin_name)
  70     print ("cpu fn", cpu)
  71     print ("io fn", io)
  72     name = "%s_%s" % (fn, pin)
  73     print ("name", name)
  74     sigs = []
  75
  76     if iotype in (IOType.In, IOType.Out):
  77         ps = pin.split("_")
  78         if pin == 'clock' and fn == 'sdr':
  79             cpup = cpu
  80             iop = io
  81         elif len(ps) == 2 and ps[-1].isdigit():
  82             pin, idx = ps
  83             idx = int(idx)
  84             print ("ps split", pin, idx)
  85             cpup = getattr(cpu, pin)[idx]
  86             iop = getattr(io, pin)[idx]
  87         elif pin.isdigit():
  88             idx = int(pin)
  89             print ("digit", idx)
  90             cpup = cpu[idx]
  91             iop = io[idx]
  92         else:
  93             cpup = getattr(cpu, pin)
  94             iop = getattr(io, pin)
  95
  96     if iotype == IOType.Out:
  97         # output from the pad is routed through C4M JTAG and so
  98         # is an *INPUT* into core.  ls180soc connects this to "real" peripheral
  99         make_pad(res, True, name, "o", cpup, iop)
 100
 101     elif iotype == IOType.In:
 102         # input to the pad is routed through C4M JTAG and so
 103         # is an *OUTPUT* into core.  ls180soc connects this to "real" peripheral
 104         make_pad(res, True, name, "i", cpup, iop)
 105
 106     elif iotype == IOType.InTriOut:
 107         if fn == 'gpio': # sigh decode GPIO special-case
 108             idx = int(pin[1:])
 109             oe_idx = idx
 110         elif fn == 'sdr': # sigh
 111             idx = int(pin.split('_')[-1])
 112             oe_idx = 0
 113         else:
 114             idx = 0
 115             oe_idx = 0
 116         print ("gpio tri", fn, pin, iotype, pin_name, scan_idx, idx)
 117         cpup, iop = get_field(cpu, "i")[idx], get_field(io, "i")[idx]
 118         make_pad(res, True, name, "i", cpup, iop)
 119         cpup, iop = get_field(cpu, "o")[idx], get_field(io, "o")[idx]
 120         make_pad(res, True, name, "o", cpup, iop)
 121         cpup, iop = get_field(cpu, "oe")[oe_idx], get_field(io, "oe")[oe_idx]
 122         make_pad(res, True, name, "oe", cpup, iop)
 123
 124     if iotype in (IOType.In, IOType.InTriOut):
 125         sigs.append(("i", 1))
 126     if iotype in (IOType.Out, IOType.TriOut, IOType.InTriOut):
 127         sigs.append(("o", 1))
 128     if iotype in (IOType.TriOut, IOType.InTriOut):
 129         sigs.append(("oe", 1))
 130
 131
 132 class LibreSoC(CPU):
 133     name                 = "libre_soc"
 134     human_name           = "Libre-SoC"
 135     variants             = CPU_VARIANTS
 136     endianness           = "little"
 137     gcc_triple           = ("powerpc64le-linux", "powerpc64le-linux-gnu")
 138     linker_output_format = "elf64-powerpcle"
 139     nop                  = "nop"
 140     io_regions           = {0xc0000000: 0x10000000} # origin, length
 141
 142     @property
 143     def mem_map(self):
 144         return {"csr": 0xc0000000}
 145
 146     @property
 147     def gcc_flags(self):
 148         flags  = "-m64 "
 149         flags += "-mabi=elfv2 "
 150         flags += "-msoft-float "
 151         flags += "-mno-string "
 152         flags += "-mno-multiple "
 153         flags += "-mno-vsx "
 154         flags += "-mno-altivec "
 155         flags += "-mlittle-endian "
 156         flags += "-mstrict-align "
 157         flags += "-fno-stack-protector "
 158         flags += "-mcmodel=small "
 159         flags += "-D__microwatt__ "
 160         return flags
 161
 162     def __init__(self, platform, variant="standard"):
 163         self.platform     = platform
 164         self.variant      = variant
 165         self.reset        = Signal()
 166
 167         irq_en = "noirq" not in variant
 168
 169         if irq_en:
 170             self.interrupt    = Signal(16)
 171
 172         if variant == "standard32":
 173             self.data_width           = 32
 174             self.dbus = dbus = wb.Interface(data_width=32, adr_width=30)
 175         else:
 176             self.dbus = dbus = wb.Interface(data_width=64, adr_width=29)
 177             self.data_width           = 64
 178         self.ibus = ibus = wb.Interface(data_width=64, adr_width=29)
 179
 180         self.xics_icp = icp = wb.Interface(data_width=32, adr_width=30)
 181         self.xics_ics = ics = wb.Interface(data_width=32, adr_width=30)
 182
 183         jtag_en = ('jtag' in variant) or variant == 'ls180'
 184
 185         if "testgpio" in variant:
 186             self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
 187         if jtag_en:
 188             self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)
 189
 190         if "sram4k" in variant or variant == 'ls180':
 191             self.srams = srams = []
 192             for i in range(4):
 193                 srams.append(wb.Interface(data_width=64, adr_width=29))
 194
 195         self.periph_buses = [ibus, dbus]
 196         self.memory_buses = []
 197
 198         if jtag_en:
 199             self.periph_buses.append(jtag_wb)
 200             self.jtag_tck = Signal(1)
 201             self.jtag_tms = Signal(1)
 202             self.jtag_tdi = Signal(1)
 203             self.jtag_tdo = Signal(1)
 204         else:
 205             self.dmi_addr = Signal(4)
 206             self.dmi_din = Signal(64)
 207             self.dmi_dout = Signal(64)
 208             self.dmi_wr = Signal(1)
 209             self.dmi_ack = Signal(1)
 210             self.dmi_req = Signal(1)
 211
 212         # # #
 213
 214         self.cpu_params = dict(
 215             # Clock / Reset
 216             i_clk              = ClockSignal(),
 217             i_rst              = ResetSignal() | self.reset,
 218
 219             # Monitoring / Debugging
 220             i_pc_i             = 0,
 221             i_pc_i_ok          = 0,
 222             i_core_bigendian_i = 0, # Signal(),
 223             o_busy_o           = Signal(),   # not connected
 224             o_memerr_o         = Signal(),   # not connected
 225             o_pc_o             = Signal(64), # not connected
 226         )
 227
 228         if irq_en:
 229             # interrupts
 230             self.cpu_params['i_int_level_i'] = self.interrupt
 231
 232         if jtag_en:
 233             self.cpu_params.update(dict(
 234                 # JTAG Debug bus
 235                 o_TAP_bus__tdo = self.jtag_tdo,
 236                 i_TAP_bus__tdi = self.jtag_tdi,
 237                 i_TAP_bus__tms = self.jtag_tms,
 238                 i_TAP_bus__tck = self.jtag_tck,
 239             ))
 240         else:
 241             self.cpu_params.update(dict(
 242                 # DMI Debug bus
 243                 i_dmi_addr_i          = self.dmi_addr,
 244                 i_dmi_din             = self.dmi_din,
 245                 o_dmi_dout            = self.dmi_dout,
 246                 i_dmi_req_i           = self.dmi_req,
 247                 i_dmi_we_i            = self.dmi_wr,
 248                 o_dmi_ack_o           = self.dmi_ack,
 249             ))
 250
 251         # add clock select, pll output
 252         if variant == "ls180":
 253             self.pll_18_o = Signal()
 254             self.clk_sel = Signal(2)
 255             self.pll_lck_o = Signal()
 256             self.cpu_params['i_clk_sel_i'] = self.clk_sel
 257             self.cpu_params['o_pll_18_o'] = self.pll_18_o
 258             self.cpu_params['o_pll_lck_o'] = self.pll_lck_o
 259
 260         # add wishbone buses to cpu params
 261         self.cpu_params.update(make_wb_bus("ibus", ibus, True))
 262         self.cpu_params.update(make_wb_bus("dbus", dbus, True))
 263         self.cpu_params.update(make_wb_slave("ics_wb", ics, True))
 264         self.cpu_params.update(make_wb_slave("icp_wb", icp, True))
 265         if "testgpio" in variant:
 266             self.cpu_params.update(make_wb_slave("gpio_wb", gpio))
 267         if jtag_en:
 268             self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))
 269         if "sram4k" in variant or variant == 'ls180':
 270             for i, sram in enumerate(srams):
 271                 self.cpu_params.update(make_wb_slave("sram4k_%d_wb" % i, sram))
 272
 273         # and set ibus advanced tags to zero (disable)
 274         self.cpu_params['i_ibus__cti'] = 0
 275         self.cpu_params['i_ibus__bte'] = 0
 276         self.cpu_params['i_dbus__cti'] = 0
 277         self.cpu_params['i_dbus__bte'] = 0
 278
 279         if variant == 'ls180':
 280             # urr yuk.  have to expose iopads / pins from core to litex
 281             # then back again.  cut _some_ of that out by connecting
 282             self.padresources = io()
 283             self.pad_cm = ConstraintManager(self.padresources, [])
 284             self.cpupads = {}
 285             iopads = {}
 286             litexmap = {}
 287             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
 288                       'pwm', 'sd0', 'sdr'}
 289             for periph in subset:
 290                 origperiph = periph
 291                 num = None
 292                 if periph[-1].isdigit():
 293                     periph, num = periph[:-1], int(periph[-1])
 294                 print ("periph request", periph, num)
 295                 if periph == 'mspi':
 296                     if num == 0:
 297                         periph, num = 'spimaster', None
 298                     else:
 299                         periph, num = 'spisdcard', None
 300                 elif periph == 'sdr':
 301                     periph = 'sdram'
 302                 elif periph == 'mtwi':
 303                     periph = 'i2c'
 304                 elif periph == 'sd':
 305                     periph, num = 'sdcard', None
 306                 litexmap[origperiph] = (periph, num)
 307                 self.cpupads[origperiph] = platform.request(periph, num)
 308                 iopads[origperiph] = self.pad_cm.request(periph, num)
 309                 if periph == 'sdram':
 310                     # special-case sdram clock
 311                     ck = platform.request("sdram_clock")
 312                     self.cpupads['sdram_clock'] = ck
 313                     ck = self.pad_cm.request("sdram_clock")
 314                     iopads['sdram_clock'] = ck
 315
 316             pinset = get_pinspecs(subset=subset)
 317             p = Pins(pinset)
 318             for pin in list(p):
 319                 make_jtag_ioconn(self.cpu_params, pin, self.cpupads, iopads)
 320
 321         # add verilog sources
 322         self.add_sources(platform)
 323
 324     def set_reset_address(self, reset_address):
 325         assert not hasattr(self, "reset_address")
 326         self.reset_address = reset_address
 327         assert reset_address == 0x00000000
 328
 329     @staticmethod
 330     def add_sources(platform):
 331         cdir = os.path.dirname(__file__)
 332         platform.add_source(os.path.join(cdir, "libresoc.v"))
 333
 334     def do_finalize(self):
 335         self.specials += Instance("test_issuer", **self.cpu_params)
 336