git.libre-soc.org Git - soc.git/history - src/soc/regfile/sram

2022-04-03	Cesar Strauss	Extend the proof to a non-transparent port	blob \| commitdiff \| raw
2022-04-03	Cesar Strauss	Run formal proof on both types (even/odd) of phased...	blob \| commitdiff \| raw \| diff to current
2022-04-03	Cesar Strauss	Complete the formal proof of the pseudo dual port SRAM	blob \| commitdiff \| raw \| diff to current
2022-04-03	Cesar Strauss	Implement a debug port on the pseudo 1W/1R SRAM	blob \| commitdiff \| raw \| diff to current
2022-04-03	Cesar Strauss	Formal proof of the phased write dual port memory wrapper	blob \| commitdiff \| raw \| diff to current
2022-04-02	Cesar Strauss	Implement transparent read ports on the phased write...	blob \| commitdiff \| raw \| diff to current
2022-04-02	Cesar Strauss	Implement and test a "phased write port" memory	blob \| commitdiff \| raw \| diff to current
2022-03-27	Cesar Strauss	Finish the SRAM formal proof by implementing induction	blob \| commitdiff \| raw \| diff to current
2022-03-26	Cesar Strauss	Add formal verification of the single port memory block	blob \| commitdiff \| raw \| diff to current
2022-03-13	Cesar Strauss	Simulate some read/write/modify operations on the SRAM...	blob \| commitdiff \| raw \| diff to current
2022-03-13	Cesar Strauss	Add a Single R/W Port SRAM model	blob \| commitdiff \| raw \| diff to current