properly set the number of integer ALUs (2 at the moment)
[soc.git] / src /
2019-05-24 Luke Kenneth Casso... make bgt accessible outside of CU
2019-05-24 Luke Kenneth Casso... check that bgt test ALU works
2019-05-24 Luke Kenneth Casso... add delay on branches
2019-05-24 Luke Kenneth Casso... remove unneeded code
2019-05-24 Luke Kenneth Casso... add delay on branches
2019-05-24 Luke Kenneth Casso... work on branch simulation logic
2019-05-24 Luke Kenneth Casso... reset shadow latches if neither success nor fail are...
2019-05-24 Luke Kenneth Casso... split out shared wait for issue and wait for busy clear...
2019-05-24 Luke Kenneth Casso... make a start on a branch simulator
2019-05-24 Luke Kenneth Casso... add simple branch-compare example ALU
2019-05-24 Luke Kenneth Casso... add priority picker docstring
2019-05-24 Luke Kenneth Casso... cleanup, docstrings
2019-05-23 Luke Kenneth Casso... shadow seems to do the job of guaranteeing write-after...
2019-05-23 Luke Kenneth Casso... set up the shadow grid
2019-05-23 Luke Kenneth Casso... only want a single-bit transition
2019-05-23 Luke Kenneth Casso... add in busy_prev/next signal to work out which unit...
2019-05-23 Luke Kenneth Casso... shadow fail/good signals need to be amalgamated (shadow...
2019-05-23 Luke Kenneth Casso... make shadow inputs/good/fail arrays (actual matrix...
2019-05-23 Luke Kenneth Casso... decide to do write-after-write shadows
2019-05-23 Luke Kenneth Casso... connect FUFU/FURegs Matrices to resettable go_rd/go_wr...
2019-05-23 Luke Kenneth Casso... start wiring up shadow matrix
2019-05-23 Luke Kenneth Casso... re-enable shadow/go_die
2019-05-23 Luke Kenneth Casso... whoops disconnected go_wr from CUs by mistake
2019-05-23 Luke Kenneth Casso... add shadow matrix (unconnected)
2019-05-23 Luke Kenneth Casso... add shadow matrix, array of shadow functions
2019-05-23 Luke Kenneth Casso... add in shadown and go_die into comp unit
2019-05-23 Luke Kenneth Casso... split out shadow into separate module
2019-05-22 Luke Kenneth Casso... sort out counter, rename data_o to data_r (register...
2019-05-22 Luke Kenneth Casso... invert write pending before use
2019-05-22 Luke Kenneth Casso... testing if hazard can be done in current cycle
2019-05-22 Luke Kenneth Casso... use global pending vectors for read/write pending accum...
2019-05-22 Luke Kenneth Casso... clean up names, also note that readable is true if...
2019-05-22 Luke Kenneth Casso... use shifter opcode
2019-05-22 Luke Kenneth Casso... ignore self-to-self read and write pending hazards
2019-05-22 Luke Kenneth Casso... read-after-write self-referring hazard
2019-05-22 Luke Kenneth Casso... allow loops to run instruction batches more than once
2019-05-22 Luke Kenneth Casso... WaW needs to stall
2019-05-22 Luke Kenneth Casso... wait for busy to go LOW before ending
2019-05-22 Luke Kenneth Casso... experiment with different completion times
2019-05-22 Luke Kenneth Casso... add in 2 more ALUs, now 4x4 scoreboard
2019-05-22 Luke Kenneth Casso... add mul and shift to simulation
2019-05-22 Luke Kenneth Casso... add extra regression test
2019-05-22 Luke Kenneth Casso... add div and shift (as experiment)
2019-05-22 Luke Kenneth Casso... have to stop forward progress if issue is set
2019-05-22 Luke Kenneth Casso... random regression test shows an inter-dependency fail
2019-05-21 Luke Kenneth Casso... working on all cycles, RaW / WaR
2019-05-21 Luke Kenneth Casso... got working (sort-of) cscore6600
2019-05-21 Luke Kenneth Casso... got working (sort-of) cscore6600
2019-05-21 Luke Kenneth Casso... add read/write reg select vectors, in and out, similar...
2019-05-20 Luke Kenneth Casso... use dep cell format
2019-05-20 Luke Kenneth Casso... invert x/y in fu pending
2019-05-20 Luke Kenneth Casso... nearly there with readable/writable on FU matrix
2019-05-20 Luke Kenneth Casso... attempting to work out FU-FU matrix connections
2019-05-20 Luke Kenneth Casso... include hazard line to swap rd/wr dependencies
2019-05-19 Luke Kenneth Casso... non-overlapping instructions ok
2019-05-19 Luke Kenneth Casso... sync ok on simple add
2019-05-19 Luke Kenneth Casso... add reg clearing and read-request release
2019-05-19 Luke Kenneth Casso... use register-based DepCell
2019-05-19 Luke Kenneth Casso... creating separate dependency cell which can be used...
2019-05-19 Luke Kenneth Casso... experiment switching over fwd and rsel in dependency...
2019-05-19 Luke Kenneth Casso... add individual dependency cell (sync mode)
2019-05-19 Luke Kenneth Casso... scoreboard 6600 experimentation
2019-05-18 Luke Kenneth Casso... whoops bug where rsel lists were being re-initialised...
2019-05-18 Luke Kenneth Casso... reduce length of vectors (per-row only single bit)
2019-05-18 Luke Kenneth Casso... connect up vectors direct
2019-05-18 Luke Kenneth Casso... connect dependency row outputs
2019-05-18 Luke Kenneth Casso... compress dependency matrix outputs into a row
2019-05-18 Luke Kenneth Casso... move dependency cells to row class
2019-05-18 Luke Kenneth Casso... Revert "whoops use global vector correctly"
2019-05-18 Luke Kenneth Casso... whoops use global vector correctly
2019-05-18 Luke Kenneth Casso... whoops use global vector correctly
2019-05-18 Luke Kenneth Casso... reduce syncs, get FU-FU and FU on same clock cycle
2019-05-18 Luke Kenneth Casso... now using readable/writable from fu-fu matrix, seems...
2019-05-18 Luke Kenneth Casso... use FU-FU matrix, seems to be working, still have to...
2019-05-18 Luke Kenneth Casso... use FU-FU matrix, seems to be working, still have to...
2019-05-16 Luke Kenneth Casso... reorg instr test issue
2019-05-16 Luke Kenneth Casso... add back in rd-flag qualification into fn unit
2019-05-16 Luke Kenneth Casso... bring in go_rd_i into 6600 scoreboard, on 1-clock delay
2019-05-16 Luke Kenneth Casso... and in go_rd_i into group picker read
2019-05-16 Luke Kenneth Casso... remove & rd_l.q, is now in group picker
2019-05-16 Luke Kenneth Casso... add in go_rd
2019-05-16 Luke Kenneth Casso... experiment lock out of registers in read vector
2019-05-16 Luke Kenneth Casso... sync function unit src/dest
2019-05-16 Luke Kenneth Casso... getting there with instruction overlapping
2019-05-15 Luke Kenneth Casso... try random inputs
2019-05-15 Luke Kenneth Casso... write-after-read hazard working
2019-05-15 Luke Kenneth Casso... make global pending sync-delayed
2019-05-15 Luke Kenneth Casso... make fn unit invert readable, however qualify with...
2019-05-15 Luke Kenneth Casso... increase counter, experiment with longer completion...
2019-05-15 Luke Kenneth Casso... very weird: invert readable vector, cscore works
2019-05-14 Luke Kenneth Casso... experimenting with cscore, overlapping instructions
2019-05-14 Luke Kenneth Casso... inverted global write pend vector, on creation of reada...
2019-05-14 Luke Kenneth Casso... experimenting with score6600
2019-05-14 Luke Kenneth Casso... experimenting with cscore
2019-05-14 Luke Kenneth Casso... latch Function Unit registers based on "issue" signal
2019-05-13 Luke Kenneth Casso... comb on intpick
2019-05-13 Luke Kenneth Casso... score6600 working without FunctionUnit (using dep matrices)
2019-05-13 Luke Kenneth Casso... sync on req_rel
2019-05-13 Luke Kenneth Casso... return to latch on src for oper
2019-05-13 Luke Kenneth Casso... rename intermediate signals to wr_wait/rd_wait
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