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soc.git
2021-02-20 Luke Kenneth... add litex wishbone interconnect to 4x 4k SRAMs commit | commitdiff | tree
2021-02-20 Luke Kenneth... add QTY 4of 4k SRAMs SPBlock512W64B8W to TestIssuer... commit | commitdiff | tree
2021-02-20 Luke Kenneth... add option for QTY 4x 4k SRAM blocks (not added yet... commit | commitdiff | tree
2021-02-20 Luke Kenneth... add Wishbone-wrapped SPBlock_512W64B8W commit | commitdiff | tree
2021-02-20 Luke Kenneth... whoops set ROM to none by mistake commit | commitdiff | tree
2021-02-20 Luke Kenneth... whoops spelling error commit | commitdiff | tree
2021-02-20 Luke Kenneth... add (unused) code for writing out SVSTATE in TestIssuer commit | commitdiff | tree
2021-02-20 Luke Kenneth... correct arguments, set microwatt_mmu=True, pass in... commit | commitdiff | tree
2021-02-20 Luke Kenneth... minor whitespace cleanup commit | commitdiff | tree
2021-02-20 Luke Kenneth... remove massive code-duplication, move simple "self... commit | commitdiff | tree
2021-02-20 Tobias Platenmmu testcase: set MMU SPRs commit | commitdiff | tree
2021-02-20 Tobias Platenadd rom debugger commit | commitdiff | tree
2021-02-20 Tobias Platenadd mmu rom testcase commit | commitdiff | tree
2021-02-18 Tobias Platenmmu: remove TestMemory commit | commitdiff | tree
2021-02-17 Luke Kenneth... declare blank classes SPEC and EXTRA2 to add MSB-to... commit | commitdiff | tree
2021-02-17 Cesar StraussUse subfield bit selection to extract the RM SVP64... commit | commitdiff | tree
2021-02-17 Cesar StraussReplace MSB-i by symbolic subfield indices and selectors commit | commitdiff | tree
2021-02-17 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... commit | commitdiff | tree
2021-02-17 Tobias Platenadd wishbone signals to gtkwave output commit | commitdiff | tree
2021-02-17 Cesar StraussAdd the SVSTATE traces to GTKWave to allow debugging... commit | commitdiff | tree
2021-02-17 Cesar StraussInitialize the core SVSTATE from the corresponding... commit | commitdiff | tree
2021-02-17 Cesar StraussRevert "Setup SVSTATE, from the test settings, at the... commit | commitdiff | tree
2021-02-17 Cesar StraussAdd a function to select bits from a signal into a... commit | commitdiff | tree
2021-02-17 Luke Kenneth... fix reg read/write in ISACaller, PowerDecoder2 handles... commit | commitdiff | tree
2021-02-17 Cesar StraussAdd a case for checking the EXTRA field and register... commit | commitdiff | tree
2021-02-17 Cesar StraussAdd traces to debug SVP64 prefix decoding issues commit | commitdiff | tree
2021-02-17 Cesar StraussSetup SVSTATE, from the test settings, at the start commit | commitdiff | tree
2021-02-16 Cesar StraussFix MSB0 issues for SVP64 commit | commitdiff | tree
2021-02-16 Tobias Platenmmureq handling commit | commitdiff | tree
2021-02-16 Tobias Platendcache error handling commit | commitdiff | tree
2021-02-16 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... commit | commitdiff | tree
2021-02-16 Luke Kenneth... ordering wrong on svstate in ISACaller commit | commitdiff | tree
2021-02-16 Luke Kenneth... adapt botchify so it can be used for 31- or 15- etc... commit | commitdiff | tree
2021-02-16 Luke Kenneth... add indicator to PowerDecoder2 when no outputs are... commit | commitdiff | tree
2021-02-15 Cole Poirierremove file experiment/formal/proof_icache.py as it... commit | commitdiff | tree
2021-02-15 Tobias Platentest case for MMU SPRs: PID and PRTBL commit | commitdiff | tree
2021-02-15 Cesar StraussSimplify obtaining the PC from the register file commit | commitdiff | tree
2021-02-15 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... commit | commitdiff | tree
2021-02-14 Cesar StraussShow traces for the register numbers of the current... commit | commitdiff | tree
2021-02-14 Cesar StraussFix width of the "extra" input on the Extra decoder commit | commitdiff | tree
2021-02-14 Cesar StraussFix conversion to MSB0 commit | commitdiff | tree
2021-02-14 Cesar StraussRemove obsolete comment commit | commitdiff | tree
2021-02-14 Luke Kenneth... add comments to TestIssuer commit | commitdiff | tree
2021-02-14 Luke Kenneth... add srcstep onto Vectorised GPRs in PowerDecoder2 commit | commitdiff | tree
2021-02-14 Luke Kenneth... add TestRunner comments commit | commitdiff | tree
2021-02-14 Luke Kenneth... add Regfiles comments commit | commitdiff | tree
2021-02-14 Luke Kenneth... add SVSTATE reading to TestIssuer commit | commitdiff | tree
2021-02-14 Luke Kenneth... add SVSTATE to CoreState commit | commitdiff | tree
2021-02-14 Luke Kenneth... add extra FSM explanatory comments to TestIssuer commit | commitdiff | tree
2021-02-13 Luke Kenneth... use function for getting instruction from 32/64 bit... commit | commitdiff | tree
2021-02-13 Cesar StraussFetch and decode the SVP64 prefix commit | commitdiff | tree
2021-02-13 Tobias PlatenOP_TLBIE must in be instr_is_priv commit | commitdiff | tree
2021-02-13 Tobias Platenkeep commits to under 80 chars commit | commitdiff | tree
2021-02-13 Cesar StraussCheck the PC value at the end of each instruction commit | commitdiff | tree
2021-02-13 Cesar StraussSkip vector test case, and add a scalar case commit | commitdiff | tree
2021-02-13 Cesar StraussFix imports and whitespace commit | commitdiff | tree
2021-02-13 Luke Kenneth... update svp64 unit test comments commit | commitdiff | tree
2021-02-13 Tobias Platenforward microwatt mmu specific SPR: PID and PRTBL commit | commitdiff | tree
2021-02-13 Luke Kenneth... add SVP64 TestIssuer separate unit test commit | commitdiff | tree
2021-02-13 Luke Kenneth... split out TestRunner into separate module commit | commitdiff | tree
2021-02-13 Cesar StraussFix SVP64 translator to yield the unaltered instruction commit | commitdiff | tree
2021-02-12 Luke Kenneth... add one SVP64 ALU test case to get started commit | commitdiff | tree
2021-02-12 Luke Kenneth... add SVSTATE to TestCase infrastructure for use in TestI... commit | commitdiff | tree
2021-02-12 Luke Kenneth... add skip of instruction if SVSTATE.VL=0 in ISACaller commit | commitdiff | tree
2021-02-12 Luke Kenneth... validate all registers to make sure no damage occurs... commit | commitdiff | tree
2021-02-12 Luke Kenneth... add srcstep and correct PC-advancing during Sub-PC... commit | commitdiff | tree
2021-02-12 Luke Kenneth... comments commit | commitdiff | tree
2021-02-12 Luke Kenneth... add in SVSTATE.srcstep update, loop from 0 to VL-1 commit | commitdiff | tree
2021-02-12 Luke Kenneth... allow PC to update by 8 in SVP64 mode commit | commitdiff | tree
2021-02-12 Luke Kenneth... fix setting of SVSTATE.VL and MVL commit | commitdiff | tree
2021-02-12 Luke Kenneth... add in SVSTATE to ISACaller, not used, just passed in commit | commitdiff | tree
2021-02-11 Luke Kenneth... comments in TestIssuer for SVP64PrefixDecoder commit | commitdiff | tree
2021-02-10 Luke Kenneth... add svp64 reg decode detection to ISACaller output commit | commitdiff | tree
2021-02-10 Luke Kenneth... starting to add SVP64 register EXTRA-read and isvec... commit | commitdiff | tree
2021-02-10 Luke Kenneth... comment update commit | commitdiff | tree
2021-02-09 colepoirieradd missing newline at end of experiment/formal/.gitignore commit | commitdiff | tree
2021-02-09 colepoirierfix erroneous removal of proof* from experiment/formal... commit | commitdiff | tree
2021-02-07 colepoirieradd skeleton implementation of experiment/formal/proof_... commit | commitdiff | tree
2021-02-07 colepoiriericache.py fix formatting commit | commitdiff | tree
2021-02-07 colepoirierModify experiment/formal/.gitignore because was prevent... commit | commitdiff | tree
2021-02-06 Cesar StraussFix whitespace commit | commitdiff | tree
2021-02-06 Cesar StraussExtract the fetch FSM out from the main FSM commit | commitdiff | tree
2021-02-05 Tobias Platenfix hanging simulation commit | commitdiff | tree
2021-02-04 Tobias Platensrc/soc/fu/mmu/fsm.py: add debug outputs for gtkwave commit | commitdiff | tree
2021-02-04 Tobias Platenupdate test_issuer_mmu_data_path.py to handle SPRs commit | commitdiff | tree
2021-02-04 Tobias Platenpass SPR MicroOp to MMU function unit commit | commitdiff | tree
2021-02-03 Luke Kenneth... nope - need it to be zero if not identified as svp64 commit | commitdiff | tree
2021-02-03 Luke Kenneth... actually no need to mux in the svp64_rm, just the id... commit | commitdiff | tree
2021-02-03 Luke Kenneth... add SVP64PowerDecoder, extracts svp64 remap if correctl... commit | commitdiff | tree
2021-02-01 Luke Kenneth... ISACaller, in svp64 mode, read the next 32 bits when... commit | commitdiff | tree
2021-02-01 Tobias Platenextending the GTKWave document in test_issuer when... commit | commitdiff | tree
2021-02-01 Luke Kenneth... sort out SelectableInt bit-ordering for identifying... commit | commitdiff | tree
2021-02-01 Luke Kenneth... construct the assembly-code prefix and base v3.0B in... commit | commitdiff | tree
2021-02-01 Cesar StraussAdd GTKWave document to test_issuer commit | commitdiff | tree
2021-01-31 Cesar StraussFix loop test and enable it commit | commitdiff | tree
2021-01-31 Luke Kenneth... start an ISACaller SVP64 unit test commit | commitdiff | tree
2021-01-31 Luke Kenneth... test SVP64 major opcode, start checking if it is EXT001... commit | commitdiff | tree
2021-01-31 Luke Kenneth... adjusting ISACaller unit test to use ISACaller.setup_one() commit | commitdiff | tree
2021-01-31 Luke Kenneth... fix ISACaller unit test commit | commitdiff | tree
2021-01-31 Tobias Platenfix two syntax errors in src/soc/decoder/isa/caller.py commit | commitdiff | tree
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