cleanup, add example output

diff --git a/Makefile b/Makefile
index b81ad8c6f8139e32f60402a78fc50d5fe5cf50ff..57bc2b7f8b678e25d7e1818c146cf1aaf9ccd17e 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,2 +1,2 @@
 test:
-       python3 svparse.py examples/assignment.sv
+       python3 svparse.py examples/counter.sv

diff --git a/absyn.py b/absyn.py
index d52250206719fbefcd53b2dba3c660b529f8ef9a..6ccbb0529944f48fcc57d1578f573bfcd8cffd10 100644 (file)
--- a/absyn.py
+++ b/absyn.py
@@ -39,8 +39,8 @@ class Assignment:
         self.right = right
 
 class Absyn:
-    def __init__(self):
-        self.outputfile = open("output.py","w")
+    def __init__(self,outputfn):
+        self.outputfile = open(outputfn,"w")
         self.outputfile.write(preamble)
         self.assign = []
         self.ports = []
@@ -147,7 +147,12 @@ class Absyn:
         print(str(clsdecl))
         return clsdecl
 
+    def appendComments(self,data):
+        lines = data.split("\n")
+        for line in lines:
+            self.printpy("#"+line)
+
     # combinatorical assign
     def cont_assign_1(self,p):
-       print("#ASSIGN:BROKEN"+str(list(p)))
+       # print("#ASSIGN:BROKEN"+str(list(p)))
        self.assign += [Assignment(p[1],p[2],p[3])]

diff --git a/examples/counter.py b/examples/counter.py
new file mode 100644 (file)
index 0000000..a40a7ca
--- /dev/null
+++ b/examples/counter.py
@@ -0,0 +1,35 @@
+# this file has been generated by sv2nmigen
+
+from nmigen import Signal, Module, Const, Cat, Elaboratable
+
+
+
+class up_counter(Elaboratable):
+
+    def __init__(self):
+        #self.clk = Signal() # input
+        #self.reset = Signal() # input
+        self.counter = Signal() # output
+    def elaborate(self, platform=None):
+        m = Module()
+        #m.d.comb += self.counter.eq(self.counter_up)
+        m.d.comb += self.counter.eq(self.counter+1)
+        return m
+#TODO test this on an icestorm compatible FPGA
+
+#module up_counter(input logic clk,
+#                  input logic reset, 
+#                  output[3:0] counter
+#                );
+#   reg [3:0] counter_up;
+#   // up counter
+#   always @(posedge clk or posedge reset)
+#     begin
+#      if(reset)
+#        counter_up <= 4'd0;
+#      else
+#        counter_up <= counter_up + 4'd1;
+#     end 
+#   assign counter = counter_up;
+#endmodule
+#

diff --git a/parse_sv.py b/parse_sv.py
index fd25dbfc83c7179ed73af7909499cce11a80690b..4973540dc4d55dc366c0d1034203623088f90462 100644 (file)
--- a/parse_sv.py
+++ b/parse_sv.py
@@ -25,7 +25,7 @@ from lib2to3.pygram import python_symbols as syms
 
 yacc1_debug = 0
 yacc2_debug = 0
-parse_debug = 1
+parse_debug = 0
 
 from ply import yacc, lex
 

diff --git a/svparse.py b/svparse.py
index 39d8c5acf41c1a4c2a3f29f9d756ab1cfab27af4..9822485712d2ef24ce3671c733c0aedcfec34b44 100644 (file)
--- a/svparse.py
+++ b/svparse.py
@@ -5,11 +5,15 @@ import parse_sv
 import absyn
 
 from ply import *
+import os 
 
 if __name__ == '__main__':
     fname = sys.argv[1]
+    outputfn = os.path.splitext(fname)[0]+'.py'
+    print(outputfn)
     with open(fname) as f:
         data = f.read()
-        parse_sv.absyn = absyn.Absyn()
+        parse_sv.absyn = absyn.Absyn(outputfn)
         yacc.parse(data, debug=parse_sv.yacc2_debug)
         print("No Error")
+        parse_sv.absyn.appendComments(data)