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add PLL clock loop-back into CPU
[libresoc-litex.git]
/
ls180soc.py
2021-06-09
Luke Kenneth Casso...
add PLL clock loop-back into CPU
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2021-05-22
Luke Kenneth Casso...
match up PLL names
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2021-04-18
Luke Kenneth Casso...
rename PLL pins to match LIP6.fr PLL
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2021-04-18
Luke Kenneth Casso...
rename XICS memmap regions
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2021-04-18
Luke Kenneth Casso...
update to build ls180 4k SRAMs
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2021-04-05
Luke Kenneth Casso...
sort out sdr and sdmmc OE pad drive, no longer one...
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2021-04-01
Luke Kenneth Casso...
disable PLL for litex build, new variant
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2021-03-29
Luke Kenneth Casso...
must not add bus width parameter
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2021-03-28
Luke Kenneth Casso...
fix issues with port direction on several pads
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2021-03-27
Luke Kenneth Casso...
latest fighting with litex to get pad directions connec...
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2021-03-25
Luke Kenneth Casso...
debugging ls180 litex hell
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2021-03-22
Luke Kenneth Casso...
SDR pad mask output for DM
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2021-03-12
Luke Kenneth Casso...
splitting out litex files from soc repo into separate...
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