ls2.git
2 years agoeven more speedup possible on QSPI
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 22:32:27 +0000 (23:32 +0100)]
even more speedup possible on QSPI

2 years agohack offset into boot address as well
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 22:18:35 +0000 (23:18 +0100)]
hack offset into boot address as well

2 years agohmm go back to mtspr for now, also add explicit loading-offset of 0x600000
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 21:11:50 +0000 (22:11 +0100)]
hmm go back to mtspr for now, also add explicit loading-offset of 0x600000
like there is in the microwatt-verilator work

2 years agotoo big, shift down to 2MB offset
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 17:54:32 +0000 (18:54 +0100)]
too big, shift down to 2MB offset

2 years agofix coldboot to boot from return address
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 17:49:55 +0000 (18:49 +0100)]
fix coldboot to boot from return address
(head.S does mtctr %r3 then bctr)
move SPI offset to 6 mbytes
(make room in future for boot bitstream)
crank versa_ecp5 freq back to 55 mhz so as to re-activate DDR3

2 years agohmm getting flags sorted out on coldboot link
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 17:11:48 +0000 (18:11 +0100)]
hmm getting flags sorted out on coldboot link

2 years agoannoying, read from wrong offset in SPI FLASH
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 15:54:16 +0000 (16:54 +0100)]
annoying, read from wrong offset in SPI FLASH

2 years agomake DRAM init conditional on whether it is detected through SYSCON
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 15:35:26 +0000 (16:35 +0100)]
make DRAM init conditional on whether it is detected through SYSCON

2 years agoput versa_ecp5 below 50 mhz as a bodge-way to stop it trying
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 15:33:02 +0000 (16:33 +0100)]
put versa_ecp5 below 50 mhz as a bodge-way to stop it trying
to create a DDR3 peripheral.  this then activates placing an SRAM (BRAM)
at 0x0000_0000 of size 0x8000 which can be used for a micro-test of
booting from QSPI.
and 0x8000 SRAM is much easier to simulate in icarus verilog

2 years agoset start to _start in hello_world lds script
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 15:31:46 +0000 (16:31 +0100)]
set start to _start in hello_world lds script
this causes elf image to get the correct start (execution) address

2 years agosigh dump memory *at* address, not address itself
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 14:29:06 +0000 (15:29 +0100)]
sigh dump memory *at* address, not address itself
also disable HAS_DRAM check so that copying to BRAM is also fine

2 years agodump start of copied memory
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 13:38:25 +0000 (14:38 +0100)]
dump start of copied memory

2 years agospeed up QSPI by putting it into way-faster mode
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 13:19:21 +0000 (14:19 +0100)]
speed up QSPI by putting it into way-faster mode

2 years agoneed to merge in tercel flash code
Luke Kenneth Casson Leighton [Sun, 10 Apr 2022 18:26:04 +0000 (19:26 +0100)]
need to merge in tercel flash code

2 years agoRevert "Wire up missing CRG / DDR3 clock control / reset signals"
Luke Kenneth Casson Leighton [Sun, 10 Apr 2022 17:15:35 +0000 (18:15 +0100)]
Revert "Wire up missing CRG / DDR3 clock control / reset signals"

This reverts commit 19ed0026e91b2dd351fbd2d692fb2c6f45b42622.

2 years agoRevert "Put sysclk2x back under system reset control"
Luke Kenneth Casson Leighton [Sun, 10 Apr 2022 17:15:15 +0000 (18:15 +0100)]
Revert "Put sysclk2x back under system reset control"

This reverts commit 793d05f2ef2e38891a4fb2ffbd6c77631fb86873.

2 years agoattempting to sort out what looks like a stack overflow
Luke Kenneth Casson Leighton [Sun, 10 Apr 2022 16:30:04 +0000 (17:30 +0100)]
attempting to sort out what looks like a stack overflow

2 years agoPut sysclk2x back under system reset control
Raptor Engineering Development Team [Sun, 10 Apr 2022 02:15:35 +0000 (21:15 -0500)]
Put sysclk2x back under system reset control

2 years agoadd QSPI dump back in (smaller one) to check it is working
Luke Kenneth Casson Leighton [Sat, 9 Apr 2022 22:06:09 +0000 (23:06 +0100)]
add QSPI dump back in (smaller one) to check it is working

2 years agoWire up missing CRG / DDR3 clock control / reset signals
Raptor Engineering Development Team [Sat, 9 Apr 2022 20:06:12 +0000 (15:06 -0500)]
Wire up missing CRG / DDR3 clock control / reset signals

2 years agosigh use MEMORY_BASE which is at 0x0000_0000 and coincides with DRAM_BASE
Luke Kenneth Casson Leighton [Sat, 9 Apr 2022 14:21:52 +0000 (15:21 +0100)]
sigh use MEMORY_BASE which is at 0x0000_0000 and coincides with DRAM_BASE

2 years agoshuffle addresses around a bit
Luke Kenneth Casson Leighton [Sat, 9 Apr 2022 13:02:01 +0000 (14:02 +0100)]
shuffle addresses around a bit
* firmware ROM is at 0xff00_0000
* DRAM is at 0x0000_0000
* for no real reason if DRAM is not present at 0x0 an SRAM is added
* set the default coldboot compile-start address at 0xff00_0000

2 years agoadd DRAM offset into SYSCON and jump to DRAM if flash successfully
Luke Kenneth Casson Leighton [Fri, 8 Apr 2022 20:34:08 +0000 (21:34 +0100)]
add DRAM offset into SYSCON and jump to DRAM if flash successfully
returns an offset after copy

2 years agoadd ELF reading to coldboot.c, move spi address to 0xf000_000
Luke Kenneth Casson Leighton [Fri, 8 Apr 2022 20:09:20 +0000 (21:09 +0100)]
add ELF reading to coldboot.c, move spi address to 0xf000_000
and add spi read-offset to Microwatt SYSCON

2 years agoadd read of SYSCON and entry for SPIFlash
Luke Kenneth Casson Leighton [Fri, 8 Apr 2022 17:46:12 +0000 (18:46 +0100)]
add read of SYSCON and entry for SPIFlash

2 years agoup the delay-time on ddr3 reset, put loop around dram init just for fun
Luke Kenneth Casson Leighton [Fri, 8 Apr 2022 14:53:29 +0000 (15:53 +0100)]
up the delay-time on ddr3 reset, put loop around dram init just for fun

2 years agocomment/80-char limit
Luke Kenneth Casson Leighton [Fri, 8 Apr 2022 11:54:05 +0000 (12:54 +0100)]
comment/80-char limit

2 years agoUpdate coldboot DDR3 init firmware to work with latest gram changes
Raptor Engineering Development Team [Thu, 7 Apr 2022 21:36:51 +0000 (16:36 -0500)]
Update coldboot DDR3 init firmware to work with latest gram changes

2 years agoAdd an asm dump with source to the coldboot makefile
Raptor Engineering Development Team [Thu, 7 Apr 2022 21:33:51 +0000 (16:33 -0500)]
Add an asm dump with source to the coldboot makefile

Clean all files, including libgram files, when running
make clean

2 years agoEnable DDR3 using a 50MHz clock on Versa 85
Raptor Engineering Development Team [Thu, 7 Apr 2022 21:33:18 +0000 (16:33 -0500)]
Enable DDR3 using a 50MHz clock on Versa 85

2 years agoMove simulation HyperRAM pins off of DDR3 pins
Raptor Engineering Development Team [Thu, 7 Apr 2022 21:32:53 +0000 (16:32 -0500)]
Move simulation HyperRAM pins off of DDR3 pins

2 years agoFix DRAM simulation commands
Raptor Engineering Development Team [Thu, 7 Apr 2022 21:32:18 +0000 (16:32 -0500)]
Fix DRAM simulation commands

2 years agoadd QSPI support to arty_a7
Luke Kenneth Casson Leighton [Wed, 6 Apr 2022 11:28:03 +0000 (12:28 +0100)]
add QSPI support to arty_a7

2 years agoallow setting individual directions on QSPI dq0-dq3
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 19:14:10 +0000 (20:14 +0100)]
allow setting individual directions on QSPI dq0-dq3

2 years agowrite out firmware to correct location,
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 17:14:46 +0000 (18:14 +0100)]
write out firmware to correct location,
adapt to 64/32 bit output

2 years agosigh put firmware.hex qspi file in correct place
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 17:09:26 +0000 (18:09 +0100)]
sigh put firmware.hex qspi file in correct place

2 years agoincrease power-on-delay for icarus sim to allow reset to occur
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 17:08:59 +0000 (18:08 +0100)]
increase power-on-delay for icarus sim to allow reset to occur

2 years agore-enable build of firmware in sim
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 16:25:44 +0000 (17:25 +0100)]
re-enable build of firmware in sim

2 years agodisable ethmac for now, pass firmware.hex to cypress qspi model
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 16:11:46 +0000 (17:11 +0100)]
disable ethmac for now, pass firmware.hex to cypress qspi model

2 years agoredo start address of firmware so it can be specified -DBOOT_INIT_BASE
Luke Kenneth Casson Leighton [Sun, 3 Apr 2022 10:23:46 +0000 (11:23 +0100)]
redo start address of firmware so it can be specified -DBOOT_INIT_BASE

2 years agoFix SPI device simulation model MISO/MOSI wiring
Raptor Engineering Development Team [Mon, 4 Apr 2022 16:06:51 +0000 (11:06 -0500)]
Fix SPI device simulation model MISO/MOSI wiring

2 years agoAdd 10/100 MAC pins for Versa boards and enable MAC
Raptor Engineering Development Team [Sat, 2 Apr 2022 21:53:56 +0000 (16:53 -0500)]
Add 10/100 MAC pins for Versa boards and enable MAC

Tested to not interfere with main SoC in simulation,
not tested further at this point.

2 years agoreduce number of params obtained on QSPI for icarus sim
Luke Kenneth Casson Leighton [Thu, 31 Mar 2022 13:42:53 +0000 (14:42 +0100)]
reduce number of params obtained on QSPI for icarus sim

2 years agogot icarus verilog model of QSPI working and it returns the same FFFFFFF
Luke Kenneth Casson Leighton [Thu, 31 Mar 2022 13:31:08 +0000 (14:31 +0100)]
got icarus verilog model of QSPI working and it returns the same FFFFFFF

2 years agowhitespace cleanup
Luke Kenneth Casson Leighton [Thu, 31 Mar 2022 09:02:39 +0000 (10:02 +0100)]
whitespace cleanup

2 years agoFix Tercel QSPI master connections
Raptor Engineering Development Team [Thu, 31 Mar 2022 07:39:31 +0000 (02:39 -0500)]
Fix Tercel QSPI master connections

Tested to work on Raptor Versa 85 custom board
in both word and byte mode.

2 years agoremove {err} feature from Tercel
Luke Kenneth Casson Leighton [Thu, 31 Mar 2022 01:31:37 +0000 (02:31 +0100)]
remove {err} feature from Tercel

2 years agoadd err wishbone feature to Tercel
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 19:43:58 +0000 (20:43 +0100)]
add err wishbone feature to Tercel

2 years agoadd config-dump from SPI
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 19:43:44 +0000 (20:43 +0100)]
add config-dump from SPI

2 years agoremove clk from spi_flash,
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 19:40:27 +0000 (20:40 +0100)]
remove clk from spi_flash,
change cs_n to cs,
de-bork WB access with stall=cyc&~ack thing

2 years agoadd qspi module to arty_a7
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 12:45:51 +0000 (13:45 +0100)]
add qspi module to arty_a7

2 years agoquick-and-dirty QSPI read test
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 12:45:32 +0000 (13:45 +0100)]
quick-and-dirty QSPI read test

2 years agouse nmigen_boards naming conventions for SPIFlash
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 12:32:35 +0000 (13:32 +0100)]
use nmigen_boards naming conventions for SPIFlash

2 years agoupdate comments, link/setup of peripherals
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 11:52:11 +0000 (12:52 +0100)]
update comments, link/setup of peripherals
(all done manually at the moment, TODO a dev-env-setup)

2 years agoadd TODO comments about using platform.add_resources
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 11:46:57 +0000 (12:46 +0100)]
add TODO comments about using platform.add_resources

2 years agowhitespace cleanup, 80 char limit
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 11:00:54 +0000 (12:00 +0100)]
whitespace cleanup, 80 char limit

2 years agoadd patch for n25q to fix model using fork/join, should be begin/end
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 10:58:32 +0000 (11:58 +0100)]
add patch for n25q to fix model using fork/join, should be begin/end

2 years agoAdd initial integration for OpenCores 10/100 Ethernet MAC
Raptor Engineering Development Team [Tue, 29 Mar 2022 01:11:43 +0000 (20:11 -0500)]
Add initial integration for OpenCores 10/100 Ethernet MAC

2 years agoFix instructions in comment
Raptor Engineering Development Team [Mon, 28 Mar 2022 15:58:23 +0000 (10:58 -0500)]
Fix instructions in comment

2 years agoquick memory test increasing by power-2 each time shows all 32 mbytes of
Luke Kenneth Casson Leighton [Mon, 28 Mar 2022 14:16:45 +0000 (15:16 +0100)]
quick memory test increasing by power-2 each time shows all 32 mbytes of
hyperram ICs are accessible

2 years agoset reset from ResetSignal not straight to 1 for HyperRAM
Luke Kenneth Casson Leighton [Sun, 27 Mar 2022 15:32:15 +0000 (16:32 +0100)]
set reset from ResetSignal not straight to 1 for HyperRAM
put correct IOPad names into HyperRAMResource for arty a7

2 years agotry latency of 7 for winbond hyperram
Luke Kenneth Casson Leighton [Sun, 27 Mar 2022 12:21:48 +0000 (13:21 +0100)]
try latency of 7 for winbond hyperram

2 years agoadd link to Winbond HyperRAM model
Luke Kenneth Casson Leighton [Sun, 27 Mar 2022 12:21:25 +0000 (13:21 +0100)]
add link to Winbond HyperRAM model

2 years agoset upper CSns on HyperRAM to zero and set reset_n HI
Luke Kenneth Casson Leighton [Sun, 27 Mar 2022 11:07:50 +0000 (12:07 +0100)]
set upper CSns on HyperRAM to zero and set reset_n HI
fix CSn pin-pad names

2 years agoadd clock output on hyperram sim
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 22:40:47 +0000 (22:40 +0000)]
add clock output on hyperram sim

2 years agoadd all 4 CSn lines for Quad HyperRAM PMOD
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 22:40:33 +0000 (22:40 +0000)]
add all 4 CSn lines for Quad HyperRAM PMOD

2 years agogrr
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 22:18:15 +0000 (22:18 +0000)]
grr

2 years agoreduce power-on-delay bits to 2 for icarus sim ecp5
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 22:16:27 +0000 (22:16 +0000)]
reduce power-on-delay bits to 2 for icarus sim ecp5

2 years agoremove switches from hyperram iverilog test
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 21:49:14 +0000 (21:49 +0000)]
remove switches from hyperram iverilog test

2 years agoremove unneeded model variable
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 21:39:58 +0000 (21:39 +0000)]
remove unneeded model variable

2 years agoadd missing ECP5 model OBZ.v and rename testbench
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 21:36:59 +0000 (21:36 +0000)]
add missing ECP5 model OBZ.v and rename testbench

2 years agosort out platform IO pads for iverilog hyperram sim
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 21:21:48 +0000 (21:21 +0000)]
sort out platform IO pads for iverilog hyperram sim

2 years agoadd hyperram iverilog runner including s27kl0641.v model
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 20:58:45 +0000 (20:58 +0000)]
add hyperram iverilog runner including s27kl0641.v model

2 years agorename ECP5 CRG, move source, remove duplicate version
Luke Kenneth Casson Leighton [Fri, 25 Mar 2022 14:55:03 +0000 (14:55 +0000)]
rename ECP5 CRG, move source, remove duplicate version

2 years agoup arty a7 frequency to 40 mhz
Luke Kenneth Casson Leighton [Fri, 25 Mar 2022 14:53:14 +0000 (14:53 +0000)]
up arty a7 frequency to 40 mhz

2 years agoincrease time for power-on-delay to 2^25 in ECP5
Luke Kenneth Casson Leighton [Fri, 25 Mar 2022 14:53:01 +0000 (14:53 +0000)]
increase time for power-on-delay to 2^25 in ECP5

2 years agoloop-test on hyperram read/write which needs carriage-return to activate
Luke Kenneth Casson Leighton [Fri, 25 Mar 2022 14:50:22 +0000 (14:50 +0000)]
loop-test on hyperram read/write which needs carriage-return to activate

2 years agoincrease delay on ECP5 ulx3s
Luke Kenneth Casson Leighton [Thu, 24 Mar 2022 22:13:13 +0000 (22:13 +0000)]
increase delay on ECP5 ulx3s

2 years agocheck ulx3s, add CRG support for ulx3s
Luke Kenneth Casson Leighton [Thu, 24 Mar 2022 20:35:46 +0000 (20:35 +0000)]
check ulx3s, add CRG support for ulx3s

2 years agoestablish power-on reset stabilisation for Arty A7 and ECP5
Luke Kenneth Casson Leighton [Thu, 24 Mar 2022 13:28:12 +0000 (13:28 +0000)]
establish power-on reset stabilisation for Arty A7 and ECP5

2 years agoadd hack to modify VERSA_ECP5 85F platform to speed grade 7
Luke Kenneth Casson Leighton [Tue, 22 Mar 2022 17:00:39 +0000 (17:00 +0000)]
add hack to modify VERSA_ECP5 85F platform to speed grade 7

2 years agoadding hyperram for arty a7 and also adding a workaround for some stupid issues
Luke Kenneth Casson Leighton [Tue, 22 Mar 2022 16:59:31 +0000 (16:59 +0000)]
adding hyperram for arty a7 and also adding a workaround for some stupid issues

2 years agoadd microwatt hello_world source
Luke Kenneth Casson Leighton [Sun, 20 Mar 2022 13:40:58 +0000 (13:40 +0000)]
add microwatt hello_world source

2 years agocrank A7 FPGA speed down to experiment
Luke Kenneth Casson Leighton [Sun, 20 Mar 2022 13:40:47 +0000 (13:40 +0000)]
crank A7 FPGA speed down to experiment

2 years agocode-comments
Luke Kenneth Casson Leighton [Sun, 20 Mar 2022 13:19:14 +0000 (13:19 +0000)]
code-comments

2 years agofix Arty A7-100t PLL with quick demo
Luke Kenneth Casson Leighton [Sun, 20 Mar 2022 13:18:21 +0000 (13:18 +0000)]
fix Arty A7-100t PLL with quick demo

2 years agofirst cut at Arty A7 Clock-Reset-Generator with S7 PLL
Luke Kenneth Casson Leighton [Sun, 20 Mar 2022 11:34:42 +0000 (11:34 +0000)]
first cut at Arty A7 Clock-Reset-Generator with S7 PLL

2 years agobeginnings of arty a7 clock-reset-generator
Luke Kenneth Casson Leighton [Sun, 20 Mar 2022 09:56:46 +0000 (09:56 +0000)]
beginnings of arty a7 clock-reset-generator

2 years agoadd VERSA_ECP5 85F custom board
Luke Kenneth Casson Leighton [Sat, 19 Mar 2022 22:44:36 +0000 (22:44 +0000)]
add VERSA_ECP5 85F custom board

2 years agomove quick read/write test for hyperram in coldboot.c
Luke Kenneth Casson Leighton [Sat, 19 Mar 2022 20:46:31 +0000 (20:46 +0000)]
move quick read/write test for hyperram in coldboot.c

2 years agoset IO_TYPE 3.3v attribute on HyperRAM not IOSTANDARD
Luke Kenneth Casson Leighton [Sat, 19 Mar 2022 19:00:19 +0000 (19:00 +0000)]
set IO_TYPE 3.3v attribute on HyperRAM not IOSTANDARD
disable DDR3 temporarily with a hack on versa_ecp5 platform

2 years agocorrect pin names for HyperRAMResource, indent spi0 core
Luke Kenneth Casson Leighton [Sat, 19 Mar 2022 14:04:57 +0000 (14:04 +0000)]
correct pin names for HyperRAMResource, indent spi0 core

2 years agofixed hyperram pin names which was stopping verilator (and pretty much
Luke Kenneth Casson Leighton [Sat, 19 Mar 2022 12:37:33 +0000 (12:37 +0000)]
fixed hyperram pin names which was stopping verilator (and pretty much
everything) from working.  HyperRAMResource had a name "clk" as a pin
which was obviously getting merged with sys_clk, sigh

2 years agodisable hyperram for now (under investigation)
Luke Kenneth Casson Leighton [Sat, 19 Mar 2022 11:48:37 +0000 (11:48 +0000)]
disable hyperram for now (under investigation)

2 years agoadding in hyperram peripheral
Luke Kenneth Casson Leighton [Sat, 19 Mar 2022 11:28:37 +0000 (11:28 +0000)]
adding in hyperram peripheral

2 years agowhitespace / module-import / comments / tidyup
Luke Kenneth Casson Leighton [Fri, 18 Mar 2022 12:32:42 +0000 (12:32 +0000)]
whitespace / module-import / comments / tidyup

2 years agobeginning to add hyperram module
Luke Kenneth Casson Leighton [Fri, 18 Mar 2022 10:51:55 +0000 (10:51 +0000)]
beginning to add hyperram module

2 years agowhitespace cleanup and make SPI core (temporarily) optional
Luke Kenneth Casson Leighton [Fri, 18 Mar 2022 09:26:46 +0000 (09:26 +0000)]
whitespace cleanup and make SPI core (temporarily) optional
based on arctic tern fpga board. TODO: add arctic tern fpga board to
nmigen_boards

2 years agowork-in-progress on DDR3 firmware. sigh
Luke Kenneth Casson Leighton [Thu, 17 Mar 2022 13:40:09 +0000 (13:40 +0000)]
work-in-progress on DDR3 firmware. sigh

2 years agocomment about icarus verilog to speed up simulations
Luke Kenneth Casson Leighton [Thu, 17 Mar 2022 12:57:05 +0000 (12:57 +0000)]
comment about icarus verilog to speed up simulations