riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "common.h"
   5 #include "config.h"
   6 #include "sim.h"
   7 #include "disasm.h"
   8 #include <cinttypes>
   9 #include <cmath>
  10 #include <cstdlib>
  11 #include <iostream>
  12 #include <assert.h>
  13 #include <limits.h>
  14
  15 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
  16   : sim(*_sim), mmu(*_mmu), id(_id), opcode_bits(0), utidx(0)
  17 {
  18   reset(true);
  19   mmu.set_processor(this);
  20
  21   #define DECLARE_INSN(name, match, mask) \
  22     register_insn(match, mask, (insn_func_t)&processor_t::rv32_##name, (insn_func_t)&processor_t::rv64_##name);
  23   #include "opcodes.h"
  24   #undef DECLARE_INSN
  25
  26   // create microthreads
  27   for (int i=0; i<MAX_UTS; i++)
  28     uts[i] = new processor_t(&sim, &mmu, id, i);
  29 }
  30
  31 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id,
  32                          uint32_t _utidx)
  33   : sim(*_sim), mmu(*_mmu), id(_id)
  34 {
  35   reset(true);
  36   set_pcr(PCR_SR, SR_U64 | SR_EF | SR_EV);
  37   utidx = _utidx;
  38
  39   // microthreads don't possess their own microthreads
  40   for (int i=0; i<MAX_UTS; i++)
  41     uts[i] = NULL;
  42 }
  43
  44 processor_t::~processor_t()
  45 {
  46 }
  47
  48 void processor_t::reset(bool value)
  49 {
  50   if (run == !value)
  51     return;
  52   run = !value;
  53
  54   // the ISA guarantees on boot that the PC is 0x2000 and the the processor
  55   // is in supervisor mode, and in 64-bit mode, if supported, with traps
  56   // and virtual memory disabled.
  57   sr = 0;
  58   set_pcr(PCR_SR, SR_S | SR_S64 | SR_IM);
  59   pc = 0x2000;
  60
  61   // the following state is undefined upon boot-up,
  62   // but we zero it for determinism
  63   XPR.reset();
  64   FPR.reset();
  65
  66   evec = 0;
  67   epc = 0;
  68   badvaddr = 0;
  69   cause = 0;
  70   pcr_k0 = 0;
  71   pcr_k1 = 0;
  72   count = 0;
  73   compare = 0;
  74   cycle = 0;
  75   set_fsr(0);
  76
  77   // vector stuff
  78   vecbanks = 0xff;
  79   vecbanks_count = 8;
  80   utidx = -1;
  81   vlmax = 32;
  82   vl = 0;
  83   nxfpr_bank = 256;
  84   nxpr_use = 32;
  85   nfpr_use = 32;
  86 }
  87
  88 void processor_t::set_fsr(uint32_t val)
  89 {
  90   fsr = val & ~FSR_ZERO; // clear FSR bits that read as zero
  91 }
  92
  93 void processor_t::vcfg()
  94 {
  95   if (nxpr_use + nfpr_use < 2)
  96     vlmax = nxfpr_bank * vecbanks_count;
  97   else
  98     vlmax = (nxfpr_bank / (nxpr_use + nfpr_use - 1)) * vecbanks_count;
  99
 100   vlmax = std::min(vlmax, MAX_UTS);
 101 }
 102
 103 void processor_t::setvl(int vlapp)
 104 {
 105   vl = std::min(vlmax, vlapp);
 106 }
 107
 108 void processor_t::take_interrupt()
 109 {
 110   uint32_t interrupts = (sr & SR_IP) >> SR_IP_SHIFT;
 111   interrupts &= (sr & SR_IM) >> SR_IM_SHIFT;
 112
 113   if(interrupts && (sr & SR_ET))
 114     for(int i = 0; ; i++, interrupts >>= 1)
 115       if(interrupts & 1)
 116         throw interrupt_t(i);
 117 }
 118
 119 void processor_t::step(size_t n, bool noisy)
 120 {
 121   if(!run)
 122     return;
 123
 124   size_t i = 0;
 125   try
 126   {
 127     take_interrupt();
 128
 129     mmu_t& _mmu = mmu;
 130     reg_t npc = pc;
 131
 132     // execute_insn fetches and executes one instruction
 133     #define execute_insn(noisy) \
 134       do { \
 135         mmu_t::insn_fetch_t fetch = _mmu.load_insn(npc, sr & SR_EC); \
 136         if(noisy) disasm(fetch.insn, npc); \
 137         npc = fetch.func(this, fetch.insn, npc); \
 138         pc = npc; \
 139       } while(0)
 140
 141     if(noisy) for( ; i < n; i++) // print out instructions as we go
 142       execute_insn(true);
 143     else
 144     {
 145       // unrolled for speed
 146       for( ; n > 3 && i < n-3; i+=4)
 147       {
 148         execute_insn(false);
 149         execute_insn(false);
 150         execute_insn(false);
 151         execute_insn(false);
 152       }
 153       for( ; i < n; i++)
 154         execute_insn(false);
 155     }
 156   }
 157   catch(trap_t t)
 158   {
 159     // an exception occurred in the target processor
 160     take_trap(t,noisy);
 161   }
 162   catch(interrupt_t t)
 163   {
 164     take_trap((1ULL << (8*sizeof(reg_t)-1)) + t.i, noisy);
 165   }
 166   catch(vt_command_t cmd)
 167   {
 168     // this microthread has finished
 169     assert(cmd == vt_command_stop);
 170   }
 171
 172   cycle += i;
 173
 174   // update timer and possibly register a timer interrupt
 175   uint32_t old_count = count;
 176   count += i;
 177   if(old_count < compare && uint64_t(old_count) + i >= compare)
 178     set_interrupt(IRQ_TIMER, true);
 179 }
 180
 181 void processor_t::take_trap(reg_t t, bool noisy)
 182 {
 183   if(noisy)
 184   {
 185     if ((sreg_t)t < 0)
 186       fprintf(stderr, "core %3d: interrupt %d, epc 0x%016" PRIx64 "\n",
 187               id, uint8_t(t), pc);
 188     else
 189       fprintf(stderr, "core %3d: trap %s, epc 0x%016" PRIx64 "\n",
 190               id, trap_name(trap_t(t)), pc);
 191   }
 192
 193   // switch to supervisor, set previous supervisor bit, disable traps
 194   set_pcr(PCR_SR, (((sr & ~SR_ET) | SR_S) & ~SR_PS) | ((sr & SR_S) ? SR_PS : 0));
 195   cause = t;
 196   epc = pc;
 197   pc = evec;
 198   badvaddr = mmu.get_badvaddr();
 199 }
 200
 201 void processor_t::deliver_ipi()
 202 {
 203   if (run)
 204     set_pcr(PCR_CLR_IPI, 1);
 205 }
 206
 207 void processor_t::disasm(insn_t insn, reg_t pc)
 208 {
 209   // the disassembler is stateless, so we share it
 210   static disassembler disasm;
 211   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIxFAST32 ") %s\n",
 212           id, pc, insn.bits, disasm.disassemble(insn).c_str());
 213 }
 214
 215 void processor_t::set_pcr(int which, reg_t val)
 216 {
 217   switch (which)
 218   {
 219     case PCR_SR:
 220       sr = (val & ~SR_IP) | (sr & SR_IP);
 221 #ifndef RISCV_ENABLE_64BIT
 222       sr &= ~(SR_S64 | SR_U64);
 223 #endif
 224 #ifndef RISCV_ENABLE_FPU
 225       sr &= ~SR_EF;
 226 #endif
 227 #ifndef RISCV_ENABLE_RVC
 228       sr &= ~SR_EC;
 229 #endif
 230 #ifndef RISCV_ENABLE_VEC
 231       sr &= ~SR_EV;
 232 #endif
 233       sr &= ~SR_ZERO;
 234       mmu.flush_tlb();
 235       break;
 236     case PCR_EPC:
 237       epc = val;
 238       break;
 239     case PCR_EVEC:
 240       evec = val;
 241       break;
 242     case PCR_COUNT:
 243       count = val;
 244       break;
 245     case PCR_COMPARE:
 246       set_interrupt(IRQ_TIMER, false);
 247       compare = val;
 248       break;
 249     case PCR_PTBR:
 250       mmu.set_ptbr(val);
 251       break;
 252     case PCR_SEND_IPI:
 253       sim.send_ipi(val);
 254       break;
 255     case PCR_CLR_IPI:
 256       set_interrupt(IRQ_IPI, val & 1);
 257       break;
 258     case PCR_K0:
 259       pcr_k0 = val;
 260       break;
 261     case PCR_K1:
 262       pcr_k1 = val;
 263       break;
 264     case PCR_VECBANK:
 265       vecbanks = val & 0xff;
 266       vecbanks_count = __builtin_popcountll(vecbanks);
 267       break;
 268     case PCR_TOHOST:
 269       if (tohost == 0)
 270         tohost = val;
 271       break;
 272     case PCR_FROMHOST:
 273       set_interrupt(IRQ_HOST, val != 0);
 274       fromhost = val;
 275       break;
 276   }
 277 }
 278
 279 reg_t processor_t::get_pcr(int which)
 280 {
 281   switch (which)
 282   {
 283     case PCR_SR:
 284       return sr;
 285     case PCR_EPC:
 286       return epc;
 287     case PCR_BADVADDR:
 288       return badvaddr;
 289     case PCR_EVEC:
 290       return evec;
 291     case PCR_COUNT:
 292       return count;
 293     case PCR_COMPARE:
 294       return compare;
 295     case PCR_CAUSE:
 296       return cause;
 297     case PCR_PTBR:
 298       return mmu.get_ptbr();
 299     case PCR_COREID:
 300       return id;
 301     case PCR_IMPL:
 302       return 1;
 303     case PCR_K0:
 304       return pcr_k0;
 305     case PCR_K1:
 306       return pcr_k1;
 307     case PCR_VECBANK:
 308       return vecbanks;
 309     case PCR_VECCFG:
 310       return nfpr_use << 18 | nxpr_use << 12 | vl;
 311     case PCR_TOHOST:
 312       return tohost;
 313     case PCR_FROMHOST:
 314       return fromhost;
 315   }
 316   return -1;
 317 }
 318
 319 void processor_t::set_interrupt(int which, bool on)
 320 {
 321   uint32_t mask = (1 << (which + SR_IP_SHIFT)) & SR_IP;
 322   if (on)
 323     sr |= mask;
 324   else
 325     sr &= ~mask;
 326 }
 327
 328 insn_func_t processor_t::decode_insn(insn_t insn)
 329 {
 330   bool rv64 = (sr & SR_S) ? (sr & SR_S64) : (sr & SR_U64);
 331
 332   auto key = insn.bits & ((1L << opcode_bits)-1);
 333   auto it = opcode_map.find(key);
 334   for (auto it = opcode_map.find(key); it != opcode_map.end() && it->first == key; ++it)
 335     if ((insn.bits & it->second.mask) == it->second.match)
 336       return rv64 ? it->second.rv64 : it->second.rv32;
 337
 338   return &processor_t::illegal_instruction;
 339 }
 340
 341 reg_t processor_t::illegal_instruction(insn_t insn, reg_t pc)
 342 {
 343   throw trap_illegal_instruction;
 344 }
 345
 346 void processor_t::register_insn(uint32_t match, uint32_t mask, insn_func_t rv32, insn_func_t rv64)
 347 {
 348   assert(mask & 1);
 349   if (opcode_bits == 0 || (mask & ((1L << opcode_bits)-1)) != ((1L << opcode_bits)-1))
 350   {
 351     unsigned x = 0;
 352     while ((mask & ((1L << (x+1))-1)) == ((1L << (x+1))-1) &&
 353            (opcode_bits == 0 || x <= opcode_bits))
 354       x++;
 355     opcode_bits = x;
 356
 357     decltype(opcode_map) new_map;
 358     for (auto it = opcode_map.begin(); it != opcode_map.end(); ++it)
 359       new_map.insert(std::make_pair(it->second.match & ((1L<<x)-1), it->second));
 360     opcode_map = new_map;
 361   }
 362
 363   opcode_map.insert(std::make_pair(match & ((1L<<opcode_bits)-1),
 364     (opcode_map_entry_t){match, mask, rv32, rv64}));
 365 }