1 // See LICENSE for license details.
10 #include "gdbserver.h"
23 processor_t::processor_t(const char* isa
, sim_t
* sim
, uint32_t id
,
25 : debug(false), sim(sim
), ext(NULL
), id(id
), halt_on_reset(halt_on_reset
)
27 parse_isa_string(isa
);
28 register_base_instructions();
30 mmu
= new mmu_t(sim
, this);
31 disassembler
= new disassembler_t(max_xlen
);
36 processor_t::~processor_t()
38 #ifdef RISCV_ENABLE_HISTOGRAM
39 if (histogram_enabled
)
41 fprintf(stderr
, "PC Histogram size:%zu\n", pc_histogram
.size());
42 for (auto it
: pc_histogram
)
43 fprintf(stderr
, "%0" PRIx64
" %" PRIu64
"\n", it
.first
, it
.second
);
51 static void bad_isa_string(const char* isa
)
53 fprintf(stderr
, "error: bad --isa option %s\n", isa
);
57 void processor_t::parse_isa_string(const char* str
)
59 std::string lowercase
, tmp
;
60 for (const char *r
= str
; *r
; r
++)
61 lowercase
+= std::tolower(*r
);
63 const char* p
= lowercase
.c_str();
64 const char* all_subsets
= "imafdc";
69 if (strncmp(p
, "rv32", 4) == 0)
70 max_xlen
= 32, isa
= reg_t(1) << 30, p
+= 4;
71 else if (strncmp(p
, "rv64", 4) == 0)
73 else if (strncmp(p
, "rv", 2) == 0)
78 } else if (*p
== 'g') { // treat "G" as "IMAFD"
79 tmp
= std::string("imafd") + (p
+1);
81 } else if (*p
!= 'i') {
85 isa_string
= "rv" + std::to_string(max_xlen
) + p
;
86 isa
|= 1L << ('s' - 'a'); // advertise support for supervisor mode
87 isa
|= 1L << ('u' - 'a'); // advertise support for user mode
90 isa
|= 1L << (*p
- 'a');
92 if (auto next
= strchr(all_subsets
, *p
)) {
93 all_subsets
= next
+ 1;
95 } else if (*p
== 'x') {
96 const char* ext
= p
+1, *end
= ext
;
99 register_extension(find_extension(std::string(ext
, end
- ext
).c_str())());
106 if (supports_extension('D') && !supports_extension('F'))
109 // advertise support for supervisor and user modes
110 isa
|= 1L << ('s' - 'a');
111 isa
|= 1L << ('u' - 'a');
116 void state_t::reset()
118 memset(this, 0, sizeof(*this));
121 mtvec
= DEFAULT_MTVEC
;
122 load_reservation
= -1;
124 for (unsigned int i
= 0; i
< num_triggers
; i
++)
125 mcontrol
[i
].type
= 2;
128 void processor_t::set_debug(bool value
)
132 ext
->set_debug(value
);
135 void processor_t::set_histogram(bool value
)
137 histogram_enabled
= value
;
138 #ifndef RISCV_ENABLE_HISTOGRAM
140 fprintf(stderr
, "PC Histogram support has not been properly enabled;");
141 fprintf(stderr
, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
146 void processor_t::reset()
149 state
.dcsr
.halt
= halt_on_reset
;
150 halt_on_reset
= false;
151 set_csr(CSR_MSTATUS
, state
.mstatus
);
154 ext
->reset(); // reset the extension
157 // Count number of contiguous 0 bits starting from the LSB.
158 static int ctz(reg_t val
)
162 while ((val
& 1) == 0)
167 void processor_t::take_interrupt(reg_t pending_interrupts
)
169 reg_t mie
= get_field(state
.mstatus
, MSTATUS_MIE
);
170 reg_t m_enabled
= state
.prv
< PRV_M
|| (state
.prv
== PRV_M
&& mie
);
171 reg_t enabled_interrupts
= pending_interrupts
& ~state
.mideleg
& -m_enabled
;
173 reg_t sie
= get_field(state
.mstatus
, MSTATUS_SIE
);
174 reg_t s_enabled
= state
.prv
< PRV_S
|| (state
.prv
== PRV_S
&& sie
);
175 if (enabled_interrupts
== 0)
176 enabled_interrupts
= pending_interrupts
& state
.mideleg
& -s_enabled
;
178 if (enabled_interrupts
)
179 throw trap_t(((reg_t
)1 << (max_xlen
-1)) | ctz(enabled_interrupts
));
182 void processor_t::set_privilege(reg_t prv
)
184 assert(prv
<= PRV_M
);
191 void processor_t::enter_debug_mode(uint8_t cause
)
193 state
.dcsr
.cause
= cause
;
194 state
.dcsr
.prv
= state
.prv
;
195 set_privilege(PRV_M
);
196 state
.dpc
= state
.pc
;
197 state
.pc
= DEBUG_ROM_START
;
200 void processor_t::take_trap(trap_t
& t
, reg_t epc
)
203 fprintf(stderr
, "core %3d: exception %s, epc 0x%016" PRIx64
"\n",
206 fprintf(stderr
, "core %3d: badaddr 0x%016" PRIx64
"\n", id
,
210 if (t
.cause() == CAUSE_BREAKPOINT
&& (
211 (state
.prv
== PRV_M
&& state
.dcsr
.ebreakm
) ||
212 (state
.prv
== PRV_H
&& state
.dcsr
.ebreakh
) ||
213 (state
.prv
== PRV_S
&& state
.dcsr
.ebreaks
) ||
214 (state
.prv
== PRV_U
&& state
.dcsr
.ebreaku
))) {
215 enter_debug_mode(DCSR_CAUSE_SWBP
);
219 if (state
.dcsr
.cause
) {
220 state
.pc
= DEBUG_ROM_EXCEPTION
;
224 // by default, trap to M-mode, unless delegated to S-mode
225 reg_t bit
= t
.cause();
226 reg_t deleg
= state
.medeleg
;
227 if (bit
& ((reg_t
)1 << (max_xlen
-1)))
228 deleg
= state
.mideleg
, bit
&= ~((reg_t
)1 << (max_xlen
-1));
229 if (state
.prv
<= PRV_S
&& bit
< max_xlen
&& ((deleg
>> bit
) & 1)) {
230 // handle the trap in S-mode
231 state
.pc
= state
.stvec
;
232 state
.scause
= t
.cause();
235 state
.sbadaddr
= t
.get_badaddr();
237 reg_t s
= state
.mstatus
;
238 s
= set_field(s
, MSTATUS_SPIE
, get_field(s
, MSTATUS_UIE
<< state
.prv
));
239 s
= set_field(s
, MSTATUS_SPP
, state
.prv
);
240 s
= set_field(s
, MSTATUS_SIE
, 0);
241 set_csr(CSR_MSTATUS
, s
);
242 set_privilege(PRV_S
);
244 state
.pc
= state
.mtvec
;
246 state
.mcause
= t
.cause();
248 state
.mbadaddr
= t
.get_badaddr();
250 reg_t s
= state
.mstatus
;
251 s
= set_field(s
, MSTATUS_MPIE
, get_field(s
, MSTATUS_UIE
<< state
.prv
));
252 s
= set_field(s
, MSTATUS_MPP
, state
.prv
);
253 s
= set_field(s
, MSTATUS_MIE
, 0);
254 set_csr(CSR_MSTATUS
, s
);
255 set_privilege(PRV_M
);
258 yield_load_reservation();
261 void processor_t::disasm(insn_t insn
)
263 uint64_t bits
= insn
.bits() & ((1ULL << (8 * insn_length(insn
.bits()))) - 1);
264 fprintf(stderr
, "core %3d: 0x%016" PRIx64
" (0x%08" PRIx64
") %s\n",
265 id
, state
.pc
, bits
, disassembler
->disassemble(insn
).c_str());
268 int processor_t::paddr_bits()
270 assert(xlen
== max_xlen
);
271 return max_xlen
== 64 ? 50 : 34;
274 void processor_t::set_csr(int which
, reg_t val
)
276 val
= zext_xlen(val
);
277 reg_t delegable_ints
= MIP_SSIP
| MIP_STIP
| MIP_SEIP
| (1 << IRQ_COP
);
278 reg_t all_ints
= delegable_ints
| MIP_MSIP
| MIP_MTIP
;
283 state
.fflags
= val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
);
287 state
.frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
291 state
.fflags
= (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
;
292 state
.frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
295 if ((val
^ state
.mstatus
) &
296 (MSTATUS_MPP
| MSTATUS_MPRV
| MSTATUS_PUM
| MSTATUS_MXR
))
299 reg_t mask
= MSTATUS_SIE
| MSTATUS_SPIE
| MSTATUS_MIE
| MSTATUS_MPIE
300 | MSTATUS_SPP
| MSTATUS_FS
| MSTATUS_MPRV
| MSTATUS_PUM
301 | MSTATUS_MPP
| MSTATUS_MXR
| MSTATUS_TW
| MSTATUS_TVM
302 | MSTATUS_TSR
| (ext
? MSTATUS_XS
: 0);
304 state
.mstatus
= (state
.mstatus
& ~mask
) | (val
& mask
);
306 bool dirty
= (state
.mstatus
& MSTATUS_FS
) == MSTATUS_FS
;
307 dirty
|= (state
.mstatus
& MSTATUS_XS
) == MSTATUS_XS
;
309 state
.mstatus
= set_field(state
.mstatus
, MSTATUS32_SD
, dirty
);
311 state
.mstatus
= set_field(state
.mstatus
, MSTATUS64_SD
, dirty
);
313 // spike supports the notion of xlen < max_xlen, but current priv spec
314 // doesn't provide a mechanism to run RV32 software on an RV64 machine
319 reg_t mask
= MIP_SSIP
| MIP_STIP
;
320 state
.mip
= (state
.mip
& ~mask
) | (val
& mask
);
324 state
.mie
= (state
.mie
& ~all_ints
) | (val
& all_ints
);
327 state
.mideleg
= (state
.mideleg
& ~delegable_ints
) | (val
& delegable_ints
);
331 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
332 #include "encoding.h"
334 state
.medeleg
= (state
.medeleg
& ~mask
) | (val
& mask
);
340 state
.minstret
= (state
.minstret
>> 32 << 32) | (val
& 0xffffffffU
);
342 state
.minstret
= val
;
346 state
.minstret
= (val
<< 32) | (state
.minstret
<< 32 >> 32);
349 state
.scounteren
= val
;
352 state
.mcounteren
= val
;
355 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
356 | SSTATUS_XS
| SSTATUS_PUM
;
357 return set_csr(CSR_MSTATUS
, (state
.mstatus
& ~mask
) | (val
& mask
));
360 reg_t mask
= MIP_SSIP
& state
.mideleg
;
361 return set_csr(CSR_MIP
, (state
.mip
& ~mask
) | (val
& mask
));
364 return set_csr(CSR_MIE
,
365 (state
.mie
& ~state
.mideleg
) | (val
& state
.mideleg
));
369 state
.sptbr
= val
& (SPTBR32_PPN
| SPTBR32_MODE
);
370 if (max_xlen
== 64 && (get_field(val
, SPTBR64_MODE
) == SPTBR_MODE_OFF
||
371 get_field(val
, SPTBR64_MODE
) == SPTBR_MODE_SV39
||
372 get_field(val
, SPTBR64_MODE
) == SPTBR_MODE_SV48
))
373 state
.sptbr
= val
& (SPTBR64_PPN
| SPTBR64_MODE
);
376 case CSR_SEPC
: state
.sepc
= val
; break;
377 case CSR_STVEC
: state
.stvec
= val
>> 2 << 2; break;
378 case CSR_SSCRATCH
: state
.sscratch
= val
; break;
379 case CSR_SCAUSE
: state
.scause
= val
; break;
380 case CSR_SBADADDR
: state
.sbadaddr
= val
; break;
381 case CSR_MEPC
: state
.mepc
= val
; break;
382 case CSR_MTVEC
: state
.mtvec
= val
>> 2 << 2; break;
383 case CSR_MSCRATCH
: state
.mscratch
= val
; break;
384 case CSR_MCAUSE
: state
.mcause
= val
; break;
385 case CSR_MBADADDR
: state
.mbadaddr
= val
; break;
387 if (!(val
& (1L << ('F' - 'A'))))
388 val
&= ~(1L << ('D' - 'A'));
390 // allow MAFDC bits in MISA to be modified
392 mask
|= 1L << ('M' - 'A');
393 mask
|= 1L << ('A' - 'A');
394 mask
|= 1L << ('F' - 'A');
395 mask
|= 1L << ('D' - 'A');
396 mask
|= 1L << ('C' - 'A');
399 isa
= (val
& mask
) | (isa
& ~mask
);
403 if (val
< state
.num_triggers
) {
409 mcontrol_t
*mc
= &state
.mcontrol
[state
.tselect
];
410 if (mc
->dmode
&& !state
.dcsr
.cause
) {
413 mc
->dmode
= get_field(val
, MCONTROL_DMODE(xlen
));
414 mc
->select
= get_field(val
, MCONTROL_SELECT
);
415 mc
->timing
= get_field(val
, MCONTROL_TIMING
);
416 mc
->action
= (mcontrol_action_t
) get_field(val
, MCONTROL_ACTION
);
417 mc
->chain
= get_field(val
, MCONTROL_CHAIN
);
418 mc
->match
= (mcontrol_match_t
) get_field(val
, MCONTROL_MATCH
);
419 mc
->m
= get_field(val
, MCONTROL_M
);
420 mc
->h
= get_field(val
, MCONTROL_H
);
421 mc
->s
= get_field(val
, MCONTROL_S
);
422 mc
->u
= get_field(val
, MCONTROL_U
);
423 mc
->execute
= get_field(val
, MCONTROL_EXECUTE
);
424 mc
->store
= get_field(val
, MCONTROL_STORE
);
425 mc
->load
= get_field(val
, MCONTROL_LOAD
);
426 // Assume we're here because of csrw.
433 if (state
.mcontrol
[state
.tselect
].dmode
&& !state
.dcsr
.cause
) {
436 if (state
.tselect
< state
.num_triggers
) {
437 state
.tdata2
[state
.tselect
] = val
;
441 state
.dcsr
.prv
= get_field(val
, DCSR_PRV
);
442 state
.dcsr
.step
= get_field(val
, DCSR_STEP
);
443 // TODO: ndreset and fullreset
444 state
.dcsr
.ebreakm
= get_field(val
, DCSR_EBREAKM
);
445 state
.dcsr
.ebreakh
= get_field(val
, DCSR_EBREAKH
);
446 state
.dcsr
.ebreaks
= get_field(val
, DCSR_EBREAKS
);
447 state
.dcsr
.ebreaku
= get_field(val
, DCSR_EBREAKU
);
448 state
.dcsr
.halt
= get_field(val
, DCSR_HALT
);
454 state
.dscratch
= val
;
459 reg_t
processor_t::get_csr(int which
)
461 uint32_t ctr_en
= -1;
462 if (state
.prv
< PRV_M
)
463 ctr_en
&= state
.mcounteren
;
464 if (state
.prv
< PRV_S
)
465 ctr_en
&= state
.scounteren
;
466 bool ctr_ok
= (ctr_en
>> (which
& 31)) & 1;
469 if (which
>= CSR_HPMCOUNTER3
&& which
<= CSR_HPMCOUNTER31
)
471 if (xlen
== 32 && which
>= CSR_HPMCOUNTER3H
&& which
<= CSR_HPMCOUNTER31H
)
474 if (which
>= CSR_MHPMCOUNTER3
&& which
<= CSR_MHPMCOUNTER31
)
476 if (xlen
== 32 && which
>= CSR_MHPMCOUNTER3H
&& which
<= CSR_MHPMCOUNTER31H
)
478 if (which
>= CSR_MHPMEVENT3
&& which
<= CSR_MHPMEVENT31
)
485 if (!supports_extension('F'))
490 if (!supports_extension('F'))
495 if (!supports_extension('F'))
497 return (state
.fflags
<< FSR_AEXC_SHIFT
) | (state
.frm
<< FSR_RD_SHIFT
);
501 return state
.minstret
;
505 return state
.minstret
;
509 return state
.minstret
>> 32;
511 case CSR_SCOUNTEREN
: return state
.scounteren
;
512 case CSR_MCOUNTEREN
: return state
.mcounteren
;
514 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
515 | SSTATUS_XS
| SSTATUS_PUM
;
516 reg_t sstatus
= state
.mstatus
& mask
;
517 if ((sstatus
& SSTATUS_FS
) == SSTATUS_FS
||
518 (sstatus
& SSTATUS_XS
) == SSTATUS_XS
)
519 sstatus
|= (xlen
== 32 ? SSTATUS32_SD
: SSTATUS64_SD
);
522 case CSR_SIP
: return state
.mip
& state
.mideleg
;
523 case CSR_SIE
: return state
.mie
& state
.mideleg
;
524 case CSR_SEPC
: return state
.sepc
;
525 case CSR_SBADADDR
: return state
.sbadaddr
;
526 case CSR_STVEC
: return state
.stvec
;
529 return state
.scause
| ((state
.scause
>> (max_xlen
-1)) << (xlen
-1));
532 if (get_field(state
.mstatus
, MSTATUS_TVM
))
533 require_privilege(PRV_M
);
535 case CSR_SSCRATCH
: return state
.sscratch
;
536 case CSR_MSTATUS
: return state
.mstatus
;
537 case CSR_MIP
: return state
.mip
;
538 case CSR_MIE
: return state
.mie
;
539 case CSR_MEPC
: return state
.mepc
;
540 case CSR_MSCRATCH
: return state
.mscratch
;
541 case CSR_MCAUSE
: return state
.mcause
;
542 case CSR_MBADADDR
: return state
.mbadaddr
;
543 case CSR_MISA
: return isa
;
544 case CSR_MARCHID
: return 0;
545 case CSR_MIMPID
: return 0;
546 case CSR_MVENDORID
: return 0;
547 case CSR_MHARTID
: return id
;
548 case CSR_MTVEC
: return state
.mtvec
;
549 case CSR_MEDELEG
: return state
.medeleg
;
550 case CSR_MIDELEG
: return state
.mideleg
;
551 case CSR_TSELECT
: return state
.tselect
;
553 if (state
.tselect
< state
.num_triggers
) {
555 mcontrol_t
*mc
= &state
.mcontrol
[state
.tselect
];
556 v
= set_field(v
, MCONTROL_TYPE(xlen
), mc
->type
);
557 v
= set_field(v
, MCONTROL_DMODE(xlen
), mc
->dmode
);
558 v
= set_field(v
, MCONTROL_MASKMAX(xlen
), mc
->maskmax
);
559 v
= set_field(v
, MCONTROL_SELECT
, mc
->select
);
560 v
= set_field(v
, MCONTROL_TIMING
, mc
->timing
);
561 v
= set_field(v
, MCONTROL_ACTION
, mc
->action
);
562 v
= set_field(v
, MCONTROL_CHAIN
, mc
->chain
);
563 v
= set_field(v
, MCONTROL_MATCH
, mc
->match
);
564 v
= set_field(v
, MCONTROL_M
, mc
->m
);
565 v
= set_field(v
, MCONTROL_H
, mc
->h
);
566 v
= set_field(v
, MCONTROL_S
, mc
->s
);
567 v
= set_field(v
, MCONTROL_U
, mc
->u
);
568 v
= set_field(v
, MCONTROL_EXECUTE
, mc
->execute
);
569 v
= set_field(v
, MCONTROL_STORE
, mc
->store
);
570 v
= set_field(v
, MCONTROL_LOAD
, mc
->load
);
577 if (state
.tselect
< state
.num_triggers
) {
578 return state
.tdata2
[state
.tselect
];
583 case CSR_TDATA3
: return 0;
587 v
= set_field(v
, DCSR_XDEBUGVER
, 1);
588 v
= set_field(v
, DCSR_NDRESET
, 0);
589 v
= set_field(v
, DCSR_FULLRESET
, 0);
590 v
= set_field(v
, DCSR_PRV
, state
.dcsr
.prv
);
591 v
= set_field(v
, DCSR_STEP
, state
.dcsr
.step
);
592 v
= set_field(v
, DCSR_DEBUGINT
, sim
->debug_module
.get_interrupt(id
));
593 v
= set_field(v
, DCSR_STOPCYCLE
, 0);
594 v
= set_field(v
, DCSR_STOPTIME
, 0);
595 v
= set_field(v
, DCSR_EBREAKM
, state
.dcsr
.ebreakm
);
596 v
= set_field(v
, DCSR_EBREAKH
, state
.dcsr
.ebreakh
);
597 v
= set_field(v
, DCSR_EBREAKS
, state
.dcsr
.ebreaks
);
598 v
= set_field(v
, DCSR_EBREAKU
, state
.dcsr
.ebreaku
);
599 v
= set_field(v
, DCSR_HALT
, state
.dcsr
.halt
);
600 v
= set_field(v
, DCSR_CAUSE
, state
.dcsr
.cause
);
606 return state
.dscratch
;
608 throw trap_illegal_instruction();
611 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
)
613 throw trap_illegal_instruction();
616 insn_func_t
processor_t::decode_insn(insn_t insn
)
618 // look up opcode in hash table
619 size_t idx
= insn
.bits() % OPCODE_CACHE_SIZE
;
620 insn_desc_t desc
= opcode_cache
[idx
];
622 if (unlikely(insn
.bits() != desc
.match
)) {
623 // fall back to linear search
624 insn_desc_t
* p
= &instructions
[0];
625 while ((insn
.bits() & p
->mask
) != p
->match
)
629 if (p
->mask
!= 0 && p
> &instructions
[0]) {
630 if (p
->match
!= (p
-1)->match
&& p
->match
!= (p
+1)->match
) {
631 // move to front of opcode list to reduce miss penalty
632 while (--p
>= &instructions
[0])
634 instructions
[0] = desc
;
638 opcode_cache
[idx
] = desc
;
639 opcode_cache
[idx
].match
= insn
.bits();
642 return xlen
== 64 ? desc
.rv64
: desc
.rv32
;
645 void processor_t::register_insn(insn_desc_t desc
)
647 instructions
.push_back(desc
);
650 void processor_t::build_opcode_map()
653 bool operator()(const insn_desc_t
& lhs
, const insn_desc_t
& rhs
) {
654 if (lhs
.match
== rhs
.match
)
655 return lhs
.mask
> rhs
.mask
;
656 return lhs
.match
> rhs
.match
;
659 std::sort(instructions
.begin(), instructions
.end(), cmp());
661 for (size_t i
= 0; i
< OPCODE_CACHE_SIZE
; i
++)
662 opcode_cache
[i
] = {0, 0, &illegal_instruction
, &illegal_instruction
};
665 void processor_t::register_extension(extension_t
* x
)
667 for (auto insn
: x
->get_instructions())
670 for (auto disasm_insn
: x
->get_disasms())
671 disassembler
->add_insn(disasm_insn
);
673 throw std::logic_error("only one extension may be registered");
675 x
->set_processor(this);
678 void processor_t::register_base_instructions()
680 #define DECLARE_INSN(name, match, mask) \
681 insn_bits_t name##_match = (match), name##_mask = (mask);
682 #include "encoding.h"
685 #define DEFINE_INSN(name) \
686 REGISTER_INSN(this, name, name##_match, name##_mask)
687 #include "insn_list.h"
690 register_insn({0, 0, &illegal_instruction
, &illegal_instruction
});
694 bool processor_t::load(reg_t addr
, size_t len
, uint8_t* bytes
)
700 memset(bytes
, 0, len
);
701 bytes
[0] = get_field(state
.mip
, MIP_MSIP
);
710 bool processor_t::store(reg_t addr
, size_t len
, const uint8_t* bytes
)
716 state
.mip
= set_field(state
.mip
, MIP_MSIP
, bytes
[0]);
725 void processor_t::trigger_updated()
728 mmu
->check_triggers_fetch
= false;
729 mmu
->check_triggers_load
= false;
730 mmu
->check_triggers_store
= false;
732 for (unsigned i
= 0; i
< state
.num_triggers
; i
++) {
733 if (state
.mcontrol
[i
].execute
) {
734 mmu
->check_triggers_fetch
= true;
736 if (state
.mcontrol
[i
].load
) {
737 mmu
->check_triggers_load
= true;
739 if (state
.mcontrol
[i
].store
) {
740 mmu
->check_triggers_store
= true;