Implement new FP encoding

[riscv-isa-sim.git] / riscv / insns / fcvt_d_w.h

diff --git a/riscv/insns/fcvt_d_w.h b/riscv/insns/fcvt_d_w.h
index 753250d6d5ea903c049c0ec7de4c53d4083b3263..4c4861c1555c48c9e136086de2890a568e9ddb2e 100644 (file)
--- a/riscv/insns/fcvt_d_w.h
+++ b/riscv/insns/fcvt_d_w.h
@@ -1,5 +1,5 @@
 require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i32_to_f64((int32_t)RS1).v);
+WRITE_FRD(i32_to_f64((int32_t)RS1));
 set_fp_exceptions;