Implement new FP encoding

https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ

diff --git a/riscv/decode.h b/riscv/decode.h
index bec548aeb835e187473b1b1d28991536d278391d..c3487b103a25906575d2806f3646f2fe6da203bb 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -17,11 +17,12 @@
 #include "encoding.h"
 #include "config.h"
 #include "common.h"
+#include "softfloat_types.h"
+#include "specialize.h"
 #include <cinttypes>
 
 typedef int64_t sreg_t;
 typedef uint64_t reg_t;
-typedef uint64_t freg_t;
 
 const int NXPR = 32;
 const int NFPR = 32;
@@ -134,7 +135,7 @@ private:
 
 #ifndef RISCV_ENABLE_COMMITLOG
 # define WRITE_REG(reg, value) STATE.XPR.write(reg, value)
-# define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, value)
+# define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, freg(value))
 #else
 # define WRITE_REG(reg, value) ({ \
     reg_t wdata = (value); /* value may have side effects */ \
@@ -142,7 +143,7 @@ private:
     STATE.XPR.write(reg, wdata); \
   })
 # define WRITE_FREG(reg, value) ({ \
-    freg_t wdata = (value); /* value may have side effects */ \
+    freg_t wdata = freg(value); /* value may have side effects */ \
     STATE.log_reg_write = (commit_log_reg_t){((reg) << 1) | 1, wdata}; \
     DO_WRITE_FREG(reg, wdata); \
   })
@@ -218,8 +219,23 @@ private:
 #define invalid_pc(pc) ((pc) & 1)
 
 /* Convenience wrappers to simplify softfloat code sequences */
-#define f32(x) ((float32_t){(uint32_t)x})
-#define f64(x) ((float64_t){(uint64_t)x})
+#define isBoxedF32(r) (((r) & 0xffffffff00000000) == 0xffffffff00000000)
+#define unboxF32(r) (isBoxedF32(r) ? (r) : defaultNaNF32UI)
+#define unboxF64(r) (r)
+struct freg_t { uint64_t v; };
+inline float32_t f32(uint32_t v) { return { v }; }
+inline float64_t f64(uint64_t v) { return { v }; }
+inline float32_t f32(freg_t r) { return f32(unboxF32(r.v)); }
+inline float64_t f64(freg_t r) { return f64(unboxF64(r.v)); }
+inline freg_t freg(float32_t f) { return { ((decltype(freg_t::v))-1 << 32) | f.v }; }
+inline freg_t freg(float64_t f) { return { f.v }; }
+inline freg_t freg(freg_t f) { return f; }
+#define F64_SIGN ((decltype(freg_t::v))1 << 63)
+#define F32_SIGN ((decltype(freg_t::v))1 << 31)
+#define fsgnj32(a, b, n, x) \
+  f32((f32(a).v & ~F32_SIGN) | ((((x) ? f32(a).v : (n) ? F32_SIGN : 0) ^ f32(b).v) & F32_SIGN))
+#define fsgnj64(a, b, n, x) \
+  f64((f64(a).v & ~F64_SIGN) | ((((x) ? f64(a).v : (n) ? F64_SIGN : 0) ^ f64(b).v) & F64_SIGN))
 
 #define validate_csr(which, write) ({ \
   if (!STATE.serialized) return PC_SERIALIZE_BEFORE; \

diff --git a/riscv/insns/c_fld.h b/riscv/insns/c_fld.h
index 10d14f86075f5385471757a523f9cdd5357e4458..319615b8e4303bf952cd0306a526f8d7fa68f5cd 100644 (file)
--- a/riscv/insns/c_fld.h
+++ b/riscv/insns/c_fld.h
@@ -1,4 +1,4 @@
 require_extension('C');
 require_extension('D');
 require_fp;
-WRITE_RVC_FRS2S(MMU.load_int64(RVC_RS1S + insn.rvc_ld_imm()));
+WRITE_RVC_FRS2S(f64(MMU.load_uint64(RVC_RS1S + insn.rvc_ld_imm())));

diff --git a/riscv/insns/c_fldsp.h b/riscv/insns/c_fldsp.h
index 8b1e19fceb1eaf15a41be2282d9f3d64ca8c7163..534eef7d2877967ca9963a5eb67dace673073435 100644 (file)
--- a/riscv/insns/c_fldsp.h
+++ b/riscv/insns/c_fldsp.h
@@ -1,4 +1,4 @@
 require_extension('C');
 require_extension('D');
 require_fp;
-WRITE_FRD(MMU.load_int64(RVC_SP + insn.rvc_ldsp_imm()));
+WRITE_FRD(f64(MMU.load_uint64(RVC_SP + insn.rvc_ldsp_imm())));

diff --git a/riscv/insns/c_flw.h b/riscv/insns/c_flw.h
index 0be27a94a4cc1d16cba37f9ac34cd38ddf258437..682566c705b764366f4681b6eff3dd85a2c27efa 100644 (file)
--- a/riscv/insns/c_flw.h
+++ b/riscv/insns/c_flw.h
@@ -2,7 +2,7 @@ require_extension('C');
 if (xlen == 32) {
   require_extension('F');
   require_fp;
-  WRITE_RVC_FRS2S(MMU.load_int32(RVC_RS1S + insn.rvc_lw_imm()));
+  WRITE_RVC_FRS2S(f32(MMU.load_uint32(RVC_RS1S + insn.rvc_lw_imm())));
 } else { // c.ld
   WRITE_RVC_RS2S(MMU.load_int64(RVC_RS1S + insn.rvc_ld_imm()));
 }

diff --git a/riscv/insns/c_flwsp.h b/riscv/insns/c_flwsp.h
index 26a47216b88cac42afca46367ba051a72758e455..79058c40a37d7b971640fc9877dc4be9ee91303b 100644 (file)
--- a/riscv/insns/c_flwsp.h
+++ b/riscv/insns/c_flwsp.h
@@ -2,7 +2,7 @@ require_extension('C');
 if (xlen == 32) {
   require_extension('F');
   require_fp;
-  WRITE_FRD(MMU.load_int32(RVC_SP + insn.rvc_lwsp_imm()));
+  WRITE_FRD(f32(MMU.load_uint32(RVC_SP + insn.rvc_lwsp_imm())));
 } else { // c.ldsp
   require(insn.rvc_rd() != 0);
   WRITE_RD(MMU.load_int64(RVC_SP + insn.rvc_ldsp_imm()));

diff --git a/riscv/insns/c_fsd.h b/riscv/insns/c_fsd.h
index 84f1a7f16f9f597c22184e91442a798dce70aa98..874326683a670e59dbfb665a0eb37a057c073d02 100644 (file)
--- a/riscv/insns/c_fsd.h
+++ b/riscv/insns/c_fsd.h
@@ -1,4 +1,4 @@
 require_extension('C');
 require_extension('D');
 require_fp;
-MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_FRS2S);
+MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_FRS2S.v);

diff --git a/riscv/insns/c_fsdsp.h b/riscv/insns/c_fsdsp.h
index 5c5c680f830569187430fcfcc7ccd5da6e4cc084..f62f8ff24c55c26d7432647267e3d3d2b7897a84 100644 (file)
--- a/riscv/insns/c_fsdsp.h
+++ b/riscv/insns/c_fsdsp.h
@@ -1,4 +1,4 @@
 require_extension('C');
 require_extension('D');
 require_fp;
-MMU.store_uint64(RVC_SP + insn.rvc_sdsp_imm(), RVC_FRS2);
+MMU.store_uint64(RVC_SP + insn.rvc_sdsp_imm(), RVC_FRS2.v);

diff --git a/riscv/insns/c_fsw.h b/riscv/insns/c_fsw.h
index 8923fef38fb1a5f88780cb1d893736809126b16a..b924a4689dc58dc4b0e7352c135d5eecefbac6d2 100644 (file)
--- a/riscv/insns/c_fsw.h
+++ b/riscv/insns/c_fsw.h
@@ -2,7 +2,7 @@ require_extension('C');
 if (xlen == 32) {
   require_extension('F');
   require_fp;
-  MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S);
+  MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S.v);
 } else { // c.sd
   MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S);
 }

diff --git a/riscv/insns/c_fswsp.h b/riscv/insns/c_fswsp.h
index c13aa12f8908c1819402319dc5c09e416420d7cf..011de555f3de08cb426f41e01b8c65931b2eca44 100644 (file)
--- a/riscv/insns/c_fswsp.h
+++ b/riscv/insns/c_fswsp.h
@@ -2,7 +2,7 @@ require_extension('C');
 if (xlen == 32) {
   require_extension('F');
   require_fp;
-  MMU.store_uint32(RVC_SP + insn.rvc_swsp_imm(), RVC_FRS2);
+  MMU.store_uint32(RVC_SP + insn.rvc_swsp_imm(), RVC_FRS2.v);
 } else { // c.sdsp
   MMU.store_uint64(RVC_SP + insn.rvc_sdsp_imm(), RVC_RS2);
 }

diff --git a/riscv/insns/fadd_d.h b/riscv/insns/fadd_d.h
index 9990174d5a48a1202058db0e129925ee55b4a85d..4a436e24874aa052d61c177c3b6a53502b6ae46d 100644 (file)
--- a/riscv/insns/fadd_d.h
+++ b/riscv/insns/fadd_d.h
@@ -1,5 +1,5 @@
 require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_add(f64(FRS1), f64(FRS2)).v);
+WRITE_FRD(f64_add(f64(FRS1), f64(FRS2)));
 set_fp_exceptions;

diff --git a/riscv/insns/fadd_s.h b/riscv/insns/fadd_s.h
index cdef36adb4a78b935018755e0901525754bc0278..cc18d58cd6f4495f40fe72c065a8f025225c7d8d 100644 (file)
--- a/riscv/insns/fadd_s.h
+++ b/riscv/insns/fadd_s.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_add(f32(FRS1), f32(FRS2)).v);
+WRITE_FRD(f32_add(f32(FRS1), f32(FRS2)));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_d_l.h b/riscv/insns/fcvt_d_l.h
index fece2277a6cf5a3359b40eaca378215f165fee02..08716cffe2d6af6f3f6844381c84b56c40e8d4fe 100644 (file)
--- a/riscv/insns/fcvt_d_l.h
+++ b/riscv/insns/fcvt_d_l.h
@@ -2,5 +2,5 @@ require_extension('D');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i64_to_f64(RS1).v);
+WRITE_FRD(i64_to_f64(RS1));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_d_lu.h b/riscv/insns/fcvt_d_lu.h
index 775c7aef2c5d361e4d6c237ce3ab1edf9eca7b81..306d7fedd8c9889f6255ab12c5da2867ac734daa 100644 (file)
--- a/riscv/insns/fcvt_d_lu.h
+++ b/riscv/insns/fcvt_d_lu.h
@@ -2,5 +2,5 @@ require_extension('D');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui64_to_f64(RS1).v);
+WRITE_FRD(ui64_to_f64(RS1));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_d_s.h b/riscv/insns/fcvt_d_s.h
index ec778cc92f475446212fca675014dff066076b26..5f805b061472c89dabdb25af51fb69a3fe1eefa1 100644 (file)
--- a/riscv/insns/fcvt_d_s.h
+++ b/riscv/insns/fcvt_d_s.h
@@ -1,5 +1,5 @@
 require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_to_f64(f32(FRS1)).v);
+WRITE_FRD(f32_to_f64(f32(FRS1)));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_d_w.h b/riscv/insns/fcvt_d_w.h
index 753250d6d5ea903c049c0ec7de4c53d4083b3263..4c4861c1555c48c9e136086de2890a568e9ddb2e 100644 (file)
--- a/riscv/insns/fcvt_d_w.h
+++ b/riscv/insns/fcvt_d_w.h
@@ -1,5 +1,5 @@
 require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i32_to_f64((int32_t)RS1).v);
+WRITE_FRD(i32_to_f64((int32_t)RS1));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_d_wu.h b/riscv/insns/fcvt_d_wu.h
index af893b32dd75352bf94c4106bfca23dcdd7c9da6..1dbf218a1cfa95a4799bb9606e0d35d3f89c9e7f 100644 (file)
--- a/riscv/insns/fcvt_d_wu.h
+++ b/riscv/insns/fcvt_d_wu.h
@@ -1,5 +1,5 @@
 require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui32_to_f64((uint32_t)RS1).v);
+WRITE_FRD(ui32_to_f64((uint32_t)RS1));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_s_d.h b/riscv/insns/fcvt_s_d.h
index 211bbba2a83f0d0a3b2698cd00e9f876cdb18fae..40333359f371b97c5fe9cda14bcdbfae5c8f3690 100644 (file)
--- a/riscv/insns/fcvt_s_d.h
+++ b/riscv/insns/fcvt_s_d.h
@@ -1,5 +1,5 @@
 require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_to_f32(f64(FRS1)).v);
+WRITE_FRD(f64_to_f32(f64(FRS1)));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_s_l.h b/riscv/insns/fcvt_s_l.h
index 1c0581a83fabef71c5f2ea34279136bd798a2993..9abcc80509eaac8d7b256e6edb98180d48659716 100644 (file)
--- a/riscv/insns/fcvt_s_l.h
+++ b/riscv/insns/fcvt_s_l.h
@@ -2,5 +2,5 @@ require_extension('F');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i64_to_f32(RS1).v);
+WRITE_FRD(i64_to_f32(RS1));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_s_lu.h b/riscv/insns/fcvt_s_lu.h
index e9bf78e0324f8abc340bb33e234473ae60845588..70c676edf410ba60fdc3be0599a03077ea8f6d48 100644 (file)
--- a/riscv/insns/fcvt_s_lu.h
+++ b/riscv/insns/fcvt_s_lu.h
@@ -2,5 +2,5 @@ require_extension('F');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui64_to_f32(RS1).v);
+WRITE_FRD(ui64_to_f32(RS1));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_s_w.h b/riscv/insns/fcvt_s_w.h
index 9411cbd59bab8fceaa8d329cbd956447426c5cea..1ddabd87c12cda406cc3e924ba9c3103815d8298 100644 (file)
--- a/riscv/insns/fcvt_s_w.h
+++ b/riscv/insns/fcvt_s_w.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i32_to_f32((int32_t)RS1).v);
+WRITE_FRD(i32_to_f32((int32_t)RS1));
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_s_wu.h b/riscv/insns/fcvt_s_wu.h
index a6cf8367f99d5a1f15b6d0e10bfdf237e053443f..c1394c3fd04af3f078f9cd29d201a52c63e199e4 100644 (file)
--- a/riscv/insns/fcvt_s_wu.h
+++ b/riscv/insns/fcvt_s_wu.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui32_to_f32((uint32_t)RS1).v);
+WRITE_FRD(ui32_to_f32((uint32_t)RS1));
 set_fp_exceptions;

diff --git a/riscv/insns/fdiv_d.h b/riscv/insns/fdiv_d.h
index d8943de7e6b3199f854e06d04a24aaa61ac61bc9..ae7911ae9ae57b314fd1bca5daba43f4af231331 100644 (file)
--- a/riscv/insns/fdiv_d.h
+++ b/riscv/insns/fdiv_d.h
@@ -1,5 +1,5 @@
 require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_div(f64(FRS1), f64(FRS2)).v);
+WRITE_FRD(f64_div(f64(FRS1), f64(FRS2)));
 set_fp_exceptions;

diff --git a/riscv/insns/fdiv_s.h b/riscv/insns/fdiv_s.h
index 66ac48da24a325c8081a8e179398b754236a6fc6..c74ff0415cb7026e58f87af4e8c9a056c6eb0310 100644 (file)
--- a/riscv/insns/fdiv_s.h
+++ b/riscv/insns/fdiv_s.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_div(f32(FRS1), f32(FRS2)).v);
+WRITE_FRD(f32_div(f32(FRS1), f32(FRS2)));
 set_fp_exceptions;

diff --git a/riscv/insns/fld.h b/riscv/insns/fld.h
index 0b50b8a5ac147dd0112f0bb9ca05c5300a532f03..4dea1d47e92476ee8de3aec2119243c566d09ee9 100644 (file)
--- a/riscv/insns/fld.h
+++ b/riscv/insns/fld.h
@@ -1,3 +1,3 @@
 require_extension('D');
 require_fp;
-WRITE_FRD(MMU.load_int64(RS1 + insn.i_imm()));
+WRITE_FRD(f64(MMU.load_uint64(RS1 + insn.i_imm())));

diff --git a/riscv/insns/flw.h b/riscv/insns/flw.h
index 489e743249a4ccb37f83c2a4960da6c7aa663529..61297544405cb65b65da17122e98247fccafa2ff 100644 (file)
--- a/riscv/insns/flw.h
+++ b/riscv/insns/flw.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-WRITE_FRD(MMU.load_uint32(RS1 + insn.i_imm()));
+WRITE_FRD(f32(MMU.load_uint32(RS1 + insn.i_imm())));

diff --git a/riscv/insns/fmadd_d.h b/riscv/insns/fmadd_d.h
index 98f1cbc25cc5b2a99b438bb8b4d1362415b72a47..ab22bebbf609948ad7f862e9391b50d86b026684 100644 (file)
--- a/riscv/insns/fmadd_d.h
+++ b/riscv/insns/fmadd_d.h
@@ -1,5 +1,5 @@
 require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(FRS3)).v);
+WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(FRS3)));
 set_fp_exceptions;

diff --git a/riscv/insns/fmadd_s.h b/riscv/insns/fmadd_s.h
index a78ed25c04c3767bca5ff8645f400698fc714c71..e919190caaa04608acc04e172614bfcd432ad2e3 100644 (file)
--- a/riscv/insns/fmadd_s.h
+++ b/riscv/insns/fmadd_s.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(FRS3)).v);
+WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(FRS3)));
 set_fp_exceptions;

diff --git a/riscv/insns/fmax_d.h b/riscv/insns/fmax_d.h
index 56c9c7a4e54a85c65e094d3146b8b490857aabbe..9c8e5b3983b470e5b85cce1f26b8e773bd8ee6e7 100644 (file)
--- a/riscv/insns/fmax_d.h
+++ b/riscv/insns/fmax_d.h
@@ -1,6 +1,6 @@
 require_extension('D');
 require_fp;
-WRITE_FRD(f64_le_quiet(f64(FRS2), f64(FRS1)) || isNaNF64UI(FRS2) ? FRS1 : FRS2);
-if ((isNaNF64UI(FRS1) && isNaNF64UI(FRS2)) || softfloat_exceptionFlags)
-  WRITE_FRD(defaultNaNF64UI);
+WRITE_FRD(f64_le_quiet(f64(FRS2), f64(FRS1)) || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
+if ((isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v)) || softfloat_exceptionFlags)
+  WRITE_FRD(f64(defaultNaNF64UI));
 set_fp_exceptions;

diff --git a/riscv/insns/fmax_s.h b/riscv/insns/fmax_s.h
index bf90356b6748c68b22dfb1f5eb4f2b2e3a64f464..2f570ead5432c040bb29459c8f84efbd4ea00e60 100644 (file)
--- a/riscv/insns/fmax_s.h
+++ b/riscv/insns/fmax_s.h
@@ -1,6 +1,6 @@
 require_extension('F');
 require_fp;
-WRITE_FRD(f32_le_quiet(f32(FRS2), f32(FRS1)) || isNaNF32UI(FRS2) ? FRS1 : FRS2);
-if ((isNaNF32UI(FRS1) && isNaNF32UI(FRS2)) || softfloat_exceptionFlags)
-  WRITE_FRD(defaultNaNF32UI);
+WRITE_FRD(f32_le_quiet(f32(FRS2), f32(FRS1)) || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
+if ((isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v)) || softfloat_exceptionFlags)
+  WRITE_FRD(f32(defaultNaNF32UI));
 set_fp_exceptions;

diff --git a/riscv/insns/fmin_d.h b/riscv/insns/fmin_d.h
index 2a1755e30eb6db78cc1a43cb91e3796344545a82..cd40e159984ab7c7953bf82aeaf213bad47b06bf 100644 (file)
--- a/riscv/insns/fmin_d.h
+++ b/riscv/insns/fmin_d.h
@@ -1,6 +1,6 @@
 require_extension('D');
 require_fp;
-WRITE_FRD(f64_lt_quiet(f64(FRS1), f64(FRS2)) || isNaNF64UI(FRS2) ? FRS1 : FRS2);
-if ((isNaNF64UI(FRS1) && isNaNF64UI(FRS2)) || softfloat_exceptionFlags)
-  WRITE_FRD(defaultNaNF64UI);
+WRITE_FRD(f64_lt_quiet(f64(FRS1), f64(FRS2)) || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
+if ((isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v)) || softfloat_exceptionFlags)
+  WRITE_FRD(f64(defaultNaNF64UI));
 set_fp_exceptions;

diff --git a/riscv/insns/fmin_s.h b/riscv/insns/fmin_s.h
index 831a7a255fed3fb8fd32083554a2255579221877..b813f45d7440cb638470e7b0f3a2e970156597bb 100644 (file)
--- a/riscv/insns/fmin_s.h
+++ b/riscv/insns/fmin_s.h
@@ -1,6 +1,6 @@
 require_extension('F');
 require_fp;
-WRITE_FRD(f32_lt_quiet(f32(FRS1), f32(FRS2)) || isNaNF32UI(FRS2) ? FRS1 : FRS2);
-if ((isNaNF32UI(FRS1) && isNaNF32UI(FRS2)) || softfloat_exceptionFlags)
-  WRITE_FRD(defaultNaNF32UI);
+WRITE_FRD(f32_lt_quiet(f32(FRS1), f32(FRS2)) || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
+if ((isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v)) || softfloat_exceptionFlags)
+  WRITE_FRD(f32(defaultNaNF32UI));
 set_fp_exceptions;

diff --git a/riscv/insns/fmsub_d.h b/riscv/insns/fmsub_d.h
index afcea88e693d77b3c90d6a7351304d29bff8e43a..5b5bc0f75e4c9c26a42b35409df98d6de063c9c3 100644 (file)
--- a/riscv/insns/fmsub_d.h
+++ b/riscv/insns/fmsub_d.h
@@ -1,5 +1,5 @@
 require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(FRS3 ^ (uint64_t)INT64_MIN)).v);
+WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(f64(FRS3).v ^ F64_SIGN)));
 set_fp_exceptions;

diff --git a/riscv/insns/fmsub_s.h b/riscv/insns/fmsub_s.h
index 45945dac4a48fd1230ddc5174e94a9915c896a24..d46c887e7c746137aebe24e64880fadb3fa34fdb 100644 (file)
--- a/riscv/insns/fmsub_s.h
+++ b/riscv/insns/fmsub_s.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(FRS3 ^ (uint32_t)INT32_MIN)).v);
+WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(f32(FRS3).v ^ F32_SIGN)));
 set_fp_exceptions;

diff --git a/riscv/insns/fmul_d.h b/riscv/insns/fmul_d.h
index 04e74025781ae817d2127174af23c16eaf25141f..9189d8d9ed4ffad7f9aff7dbc7f939076b092274 100644 (file)
--- a/riscv/insns/fmul_d.h
+++ b/riscv/insns/fmul_d.h
@@ -1,5 +1,5 @@
 require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_mul(f64(FRS1), f64(FRS2)).v);
+WRITE_FRD(f64_mul(f64(FRS1), f64(FRS2)));
 set_fp_exceptions;

diff --git a/riscv/insns/fmul_s.h b/riscv/insns/fmul_s.h
index 9ae7b3c64edbbd65c971055607937b54c0e96a9a..145d5ce4d96fcc4e9d387f9817359ea1baa6f6f9 100644 (file)
--- a/riscv/insns/fmul_s.h
+++ b/riscv/insns/fmul_s.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mul(f32(FRS1), f32(FRS2)).v);
+WRITE_FRD(f32_mul(f32(FRS1), f32(FRS2)));
 set_fp_exceptions;

diff --git a/riscv/insns/fmv_d_x.h b/riscv/insns/fmv_d_x.h
index c3f6049316b1f3be58a6d9305ba9419f913c8f20..0bff5fb7540b347aeba01b0aff264f5d922161b0 100644 (file)
--- a/riscv/insns/fmv_d_x.h
+++ b/riscv/insns/fmv_d_x.h
@@ -1,4 +1,4 @@
 require_extension('D');
 require_rv64;
 require_fp;
-WRITE_FRD(RS1);
+WRITE_FRD(f64(RS1));

diff --git a/riscv/insns/fmv_s_x.h b/riscv/insns/fmv_s_x.h
index 2daf6dabe06be573999a3f1abf6012de47904102..5f713231cb36ac3a6b32d8a6fc6276ef97b6f3db 100644 (file)
--- a/riscv/insns/fmv_s_x.h
+++ b/riscv/insns/fmv_s_x.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-WRITE_FRD(zext32(RS1));
+WRITE_FRD(f32(RS1));

diff --git a/riscv/insns/fmv_x_d.h b/riscv/insns/fmv_x_d.h
index b97d7f59bacefafcaad9f0e964b96098c8f1c0a2..da8e72a82ecd0d04eac3e9ab40e9860dcff23872 100644 (file)
--- a/riscv/insns/fmv_x_d.h
+++ b/riscv/insns/fmv_x_d.h
@@ -1,4 +1,4 @@
 require_extension('D');
 require_rv64;
 require_fp;
-WRITE_RD(FRS1);
+WRITE_RD(FRS1.v);

diff --git a/riscv/insns/fmv_x_s.h b/riscv/insns/fmv_x_s.h
index 1bee87f4aa5fa61cd98bf1a70dde5b51f9bcf169..b72247958c762237a2316ab7ed7f4a9d29eaf1fd 100644 (file)
--- a/riscv/insns/fmv_x_s.h
+++ b/riscv/insns/fmv_x_s.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-WRITE_RD(sext32(FRS1));
+WRITE_RD(sext32(FRS1.v));

diff --git a/riscv/insns/fnmadd_d.h b/riscv/insns/fnmadd_d.h
index d6e1f04ac749d27453ee10f4f2ca874a4b9e3211..e8dd743233cdf7ff7ef6dcc07231c003b8b98eb2 100644 (file)
--- a/riscv/insns/fnmadd_d.h
+++ b/riscv/insns/fnmadd_d.h
@@ -1,5 +1,5 @@
 require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_mulAdd(f64(FRS1 ^ (uint64_t)INT64_MIN), f64(FRS2), f64(FRS3 ^ (uint64_t)INT64_MIN)).v);
+WRITE_FRD(f64_mulAdd(f64(f64(FRS1).v ^ F64_SIGN), f64(FRS2), f64(f64(FRS3).v ^ F64_SIGN)));
 set_fp_exceptions;

diff --git a/riscv/insns/fnmadd_s.h b/riscv/insns/fnmadd_s.h
index 0d0b2e96bf08f6c65d76994a4431818e426ef45e..1c2996e3125909af3f6408f1798c5b717df4ae66 100644 (file)
--- a/riscv/insns/fnmadd_s.h
+++ b/riscv/insns/fnmadd_s.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(FRS1 ^ (uint32_t)INT32_MIN), f32(FRS2), f32(FRS3 ^ (uint32_t)INT32_MIN)).v);
+WRITE_FRD(f32_mulAdd(f32(f32(FRS1).v ^ F32_SIGN), f32(FRS2), f32(f32(FRS3).v ^ F32_SIGN)));
 set_fp_exceptions;

diff --git a/riscv/insns/fnmsub_d.h b/riscv/insns/fnmsub_d.h
index ee74cab2724ee190fb91b7ab58a9fc113f601233..c29a0b93ca059d7dc74cfc7e399185941bf59ecc 100644 (file)
--- a/riscv/insns/fnmsub_d.h
+++ b/riscv/insns/fnmsub_d.h
@@ -1,5 +1,5 @@
 require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_mulAdd(f64(FRS1 ^ (uint64_t)INT64_MIN), f64(FRS2), f64(FRS3)).v);
+WRITE_FRD(f64_mulAdd(f64(f64(FRS1).v ^ F64_SIGN), f64(FRS2), f64(FRS3)));
 set_fp_exceptions;

diff --git a/riscv/insns/fnmsub_s.h b/riscv/insns/fnmsub_s.h
index 3e0b8ea7ce37c85e1c6220fdefcc717e0a9cd9ba..4c61fc7c81170175929bd556095ed97481e9c135 100644 (file)
--- a/riscv/insns/fnmsub_s.h
+++ b/riscv/insns/fnmsub_s.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(FRS1 ^ (uint32_t)INT32_MIN), f32(FRS2), f32(FRS3)).v);
+WRITE_FRD(f32_mulAdd(f32(f32(FRS1).v ^ F32_SIGN), f32(FRS2), f32(FRS3)));
 set_fp_exceptions;

diff --git a/riscv/insns/fsd.h b/riscv/insns/fsd.h
index 63cc8e5fc00eae9fefaa954db7a0b09cddce3039..679cc95fb7c5fd1f28c65dcb16b18ffc25f07940 100644 (file)
--- a/riscv/insns/fsd.h
+++ b/riscv/insns/fsd.h
@@ -1,3 +1,3 @@
 require_extension('D');
 require_fp;
-MMU.store_uint64(RS1 + insn.s_imm(), FRS2);
+MMU.store_uint64(RS1 + insn.s_imm(), FRS2.v);

diff --git a/riscv/insns/fsgnj_d.h b/riscv/insns/fsgnj_d.h
index 52648a1a78649b790df944dc86f15d4d04986642..78f9ce78745c83c69b9f3df1b89a9079046e6eef 100644 (file)
--- a/riscv/insns/fsgnj_d.h
+++ b/riscv/insns/fsgnj_d.h
@@ -1,3 +1,3 @@
 require_extension('D');
 require_fp;
-WRITE_FRD((FRS1 &~ INT64_MIN) | (FRS2 & INT64_MIN));
+WRITE_FRD(fsgnj64(FRS1, FRS2, false, false));

diff --git a/riscv/insns/fsgnj_s.h b/riscv/insns/fsgnj_s.h
index 4c91ff327531125047d006ee24a563bc7b02838c..c1a70cb7979bf7be59cc299ce64f0e736a308e64 100644 (file)
--- a/riscv/insns/fsgnj_s.h
+++ b/riscv/insns/fsgnj_s.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-WRITE_FRD((FRS1 &~ (uint32_t)INT32_MIN) | (FRS2 & (uint32_t)INT32_MIN));
+WRITE_FRD(fsgnj32(FRS1, FRS2, false, false));

diff --git a/riscv/insns/fsgnjn_d.h b/riscv/insns/fsgnjn_d.h
index cdec924ba8042c4b06ad8ccbffaf0c66bc1542ae..f02c3116b78da8bc11574bab282bf2f7143a1598 100644 (file)
--- a/riscv/insns/fsgnjn_d.h
+++ b/riscv/insns/fsgnjn_d.h
@@ -1,3 +1,3 @@
 require_extension('D');
 require_fp;
-WRITE_FRD((FRS1 &~ INT64_MIN) | ((~FRS2) & INT64_MIN));
+WRITE_FRD(fsgnj64(FRS1, FRS2, true, false));

diff --git a/riscv/insns/fsgnjn_s.h b/riscv/insns/fsgnjn_s.h
index f91a7b0a43c72482d9c8600e5678c8590a5986ad..35906d6576159d47311f27dbe8debfde6c07446e 100644 (file)
--- a/riscv/insns/fsgnjn_s.h
+++ b/riscv/insns/fsgnjn_s.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-WRITE_FRD((FRS1 &~ (uint32_t)INT32_MIN) | ((~FRS2) & (uint32_t)INT32_MIN));
+WRITE_FRD(fsgnj32(FRS1, FRS2, true, false));

diff --git a/riscv/insns/fsgnjx_d.h b/riscv/insns/fsgnjx_d.h
index b09d24cb8fe48b9394e2589afc165b2ef717ccf5..c12173719b79c51d84d4a7fc9a0db5effa4aebd1 100644 (file)
--- a/riscv/insns/fsgnjx_d.h
+++ b/riscv/insns/fsgnjx_d.h
@@ -1,3 +1,3 @@
 require_extension('D');
 require_fp;
-WRITE_FRD(FRS1 ^ (FRS2 & INT64_MIN));
+WRITE_FRD(fsgnj64(FRS1, FRS2, false, true));

diff --git a/riscv/insns/fsgnjx_s.h b/riscv/insns/fsgnjx_s.h
index 1fd2de6b94b3af36241e956077050a5e77b7adc8..4d5c624b65c152b0435d1e0591732db91807d58e 100644 (file)
--- a/riscv/insns/fsgnjx_s.h
+++ b/riscv/insns/fsgnjx_s.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-WRITE_FRD(FRS1 ^ (FRS2 & (uint32_t)INT32_MIN));
+WRITE_FRD(fsgnj32(FRS1, FRS2, false, true));

diff --git a/riscv/insns/fsqrt_d.h b/riscv/insns/fsqrt_d.h
index 45f37ce00ae010d2e3b7733e7334084d0d7e9b16..da138ba1937f53070d05f81beb096a765580c457 100644 (file)
--- a/riscv/insns/fsqrt_d.h
+++ b/riscv/insns/fsqrt_d.h
@@ -1,5 +1,5 @@
 require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_sqrt(f64(FRS1)).v);
+WRITE_FRD(f64_sqrt(f64(FRS1)));
 set_fp_exceptions;

diff --git a/riscv/insns/fsqrt_s.h b/riscv/insns/fsqrt_s.h
index f3b39564f80968badfe7f7cc3f07a325665db408..747684664e7c9b7b2ac7d8abd0917aadaca041e5 100644 (file)
--- a/riscv/insns/fsqrt_s.h
+++ b/riscv/insns/fsqrt_s.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_sqrt(f32(FRS1)).v);
+WRITE_FRD(f32_sqrt(f32(FRS1)));
 set_fp_exceptions;

diff --git a/riscv/insns/fsub_d.h b/riscv/insns/fsub_d.h
index 487743e0d60826a5a9ba73e2022361c23b54f660..1418a063d6ebc1a2925e0884e1faf3c94167f92d 100644 (file)
--- a/riscv/insns/fsub_d.h
+++ b/riscv/insns/fsub_d.h
@@ -1,5 +1,5 @@
 require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_sub(f64(FRS1), f64(FRS2)).v);
+WRITE_FRD(f64_sub(f64(FRS1), f64(FRS2)));
 set_fp_exceptions;

diff --git a/riscv/insns/fsub_s.h b/riscv/insns/fsub_s.h
index e7a7cf1824ccb7e5d57575e621c39514e98e6c00..f6183ea000965c87f50db9491a9242a5139cef53 100644 (file)
--- a/riscv/insns/fsub_s.h
+++ b/riscv/insns/fsub_s.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_sub(f32(FRS1), f32(FRS2)).v);
+WRITE_FRD(f32_sub(f32(FRS1), f32(FRS2)));
 set_fp_exceptions;

diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h
index 3135e9b7dace76cc7866b46d6415965ade82a84f..42fc68373f5370635a58327a27980c9f5bfda620 100644 (file)
--- a/riscv/insns/fsw.h
+++ b/riscv/insns/fsw.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-MMU.store_uint32(RS1 + insn.s_imm(), FRS2);
+MMU.store_uint32(RS1 + insn.s_imm(), FRS2.v);

diff --git a/riscv/interactive.cc b/riscv/interactive.cc
index ee8837522e163649268e3f74e4fb80c941420fd5..31b91622720f5f7e2efcc5fe00a41e523e5a7a00 100644 (file)
--- a/riscv/interactive.cc
+++ b/riscv/interactive.cc
@@ -66,6 +66,7 @@ void sim_t::interactive()
   funcs["r"] = funcs["run"];
   funcs["rs"] = &sim_t::interactive_run_silent;
   funcs["reg"] = &sim_t::interactive_reg;
+  funcs["freg"] = &sim_t::interactive_freg;
   funcs["fregs"] = &sim_t::interactive_fregs;
   funcs["fregd"] = &sim_t::interactive_fregd;
   funcs["pc"] = &sim_t::interactive_pc;
@@ -199,7 +200,7 @@ reg_t sim_t::get_reg(const std::vector<std::string>& args)
   return p->state.XPR[r];
 }
 
-reg_t sim_t::get_freg(const std::vector<std::string>& args)
+freg_t sim_t::get_freg(const std::vector<std::string>& args)
 {
   if(args.size() != 2)
     throw trap_interactive();
@@ -231,11 +232,16 @@ void sim_t::interactive_reg(const std::string& cmd, const std::vector<std::strin
 
 union fpr
 {
-  reg_t r;
+  freg_t r;
   float s;
   double d;
 };
 
+void sim_t::interactive_freg(const std::string& cmd, const std::vector<std::string>& args)
+{
+  fprintf(stderr, "0x%016" PRIx64 "\n", get_freg(args).v);
+}
+
 void sim_t::interactive_fregs(const std::string& cmd, const std::vector<std::string>& args)
 {
   fpr f;

diff --git a/riscv/sim.h b/riscv/sim.h
index 57bdf8ce8113275a20e78b786da8fa8758c59759..8586bee2cf970ee449227af57b72f6da991c5f3b 100644 (file)
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -76,6 +76,7 @@ private:
   void interactive_run_noisy(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_run_silent(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_reg(const std::string& cmd, const std::vector<std::string>& args);
+  void interactive_freg(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_fregs(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_fregd(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_pc(const std::string& cmd, const std::vector<std::string>& args);
@@ -83,7 +84,7 @@ private:
   void interactive_str(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_until(const std::string& cmd, const std::vector<std::string>& args);
   reg_t get_reg(const std::vector<std::string>& args);
-  reg_t get_freg(const std::vector<std::string>& args);
+  freg_t get_freg(const std::vector<std::string>& args);
   reg_t get_mem(const std::vector<std::string>& args);
   reg_t get_pc(const std::vector<std::string>& args);