Implement new FP encoding

[riscv-isa-sim.git] / riscv / insns / fcvt_d_wu.h

diff --git a/riscv/insns/fcvt_d_wu.h b/riscv/insns/fcvt_d_wu.h
index 4c562481e200f869f06e6c5aeaf4848331f7ed0b..1dbf218a1cfa95a4799bb9606e0d35d3f89c9e7f 100644 (file)
--- a/riscv/insns/fcvt_d_wu.h
+++ b/riscv/insns/fcvt_d_wu.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(ui32_to_f64((uint32_t)RS1));