Implement new FP encoding

[riscv-isa-sim.git] / riscv / insns / fcvt_s_d.h

diff --git a/riscv/insns/fcvt_s_d.h b/riscv/insns/fcvt_s_d.h
index e5289c4b0d1866f19744089b0d93b6ef9aef3c7a..40333359f371b97c5fe9cda14bcdbfae5c8f3690 100644 (file)
--- a/riscv/insns/fcvt_s_d.h
+++ b/riscv/insns/fcvt_s_d.h
@@ -1,4 +1,5 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_to_f32(FRS1);
+WRITE_FRD(f64_to_f32(f64(FRS1)));
 set_fp_exceptions;