Implement new FP encoding

[riscv-isa-sim.git] / riscv / insns / fcvt_s_l.h

diff --git a/riscv/insns/fcvt_s_l.h b/riscv/insns/fcvt_s_l.h
index 1c0581a83fabef71c5f2ea34279136bd798a2993..9abcc80509eaac8d7b256e6edb98180d48659716 100644 (file)
--- a/riscv/insns/fcvt_s_l.h
+++ b/riscv/insns/fcvt_s_l.h
@@ -2,5 +2,5 @@ require_extension('F');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i64_to_f32(RS1).v);
+WRITE_FRD(i64_to_f32(RS1));
 set_fp_exceptions;