Implement new FP encoding

[riscv-isa-sim.git] / riscv / insns / fcvt_s_wu.h

diff --git a/riscv/insns/fcvt_s_wu.h b/riscv/insns/fcvt_s_wu.h
index abb782c38126d777928907cc3ba724215121ed49..c1394c3fd04af3f078f9cd29d201a52c63e199e4 100644 (file)
--- a/riscv/insns/fcvt_s_wu.h
+++ b/riscv/insns/fcvt_s_wu.h
@@ -1,4 +1,5 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-FRD = ui32_to_f32((uint32_t)RS1);
+WRITE_FRD(ui32_to_f32((uint32_t)RS1));
 set_fp_exceptions;