Implement new FP encoding

[riscv-isa-sim.git] / riscv / insns / fdiv_d.h

diff --git a/riscv/insns/fdiv_d.h b/riscv/insns/fdiv_d.h
index d8943de7e6b3199f854e06d04a24aaa61ac61bc9..ae7911ae9ae57b314fd1bca5daba43f4af231331 100644 (file)
--- a/riscv/insns/fdiv_d.h
+++ b/riscv/insns/fdiv_d.h
@@ -1,5 +1,5 @@
 require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_div(f64(FRS1), f64(FRS2)).v);
+WRITE_FRD(f64_div(f64(FRS1), f64(FRS2)));
 set_fp_exceptions;