Zero-extend flw, fmv_s_x instructions

[riscv-isa-sim.git] / riscv / insns / flw.h

diff --git a/riscv/insns/flw.h b/riscv/insns/flw.h
index 335fd7d23e3e4b118403e8a83055d1a86b3d3f1b..489e743249a4ccb37f83c2a4960da6c7aa663529 100644 (file)
--- a/riscv/insns/flw.h
+++ b/riscv/insns/flw.h
@@ -1,2 +1,3 @@
+require_extension('F');
 require_fp;
-FRD = mmu.load_int32(RS1+SIMM);
+WRITE_FRD(MMU.load_uint32(RS1 + insn.i_imm()));