Zero-extend flw, fmv_s_x instructions

   - This makes Spike more consistent with its zero-extending behavior
     regarding other SP operations when placed into the 64b f-registers.

diff --git a/riscv/insns/flw.h b/riscv/insns/flw.h
index b94ba5dd6e8c7958d6a24c3c5df2e93426cba42a..489e743249a4ccb37f83c2a4960da6c7aa663529 100644 (file)
--- a/riscv/insns/flw.h
+++ b/riscv/insns/flw.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-WRITE_FRD(MMU.load_int32(RS1 + insn.i_imm()));
+WRITE_FRD(MMU.load_uint32(RS1 + insn.i_imm()));

diff --git a/riscv/insns/fmv_s_x.h b/riscv/insns/fmv_s_x.h
index f0f95aca06b7bea9b73032c7a8c9f6dbe273c08f..2daf6dabe06be573999a3f1abf6012de47904102 100644 (file)
--- a/riscv/insns/fmv_s_x.h
+++ b/riscv/insns/fmv_s_x.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-WRITE_FRD(RS1);
+WRITE_FRD(zext32(RS1));