Implement new FP encoding

[riscv-isa-sim.git] / riscv / insns / fmax_d.h

diff --git a/riscv/insns/fmax_d.h b/riscv/insns/fmax_d.h
index eb156de9f0a67e00e5e8ddbe2f08e0773417a013..9c8e5b3983b470e5b85cce1f26b8e773bd8ee6e7 100644 (file)
--- a/riscv/insns/fmax_d.h
+++ b/riscv/insns/fmax_d.h
@@ -1,5 +1,6 @@
 require_extension('D');
 require_fp;
-WRITE_FRD(isNaNF64UI(FRS2) || f64_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */
-      ? FRS1 : FRS2);
+WRITE_FRD(f64_le_quiet(f64(FRS2), f64(FRS1)) || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
+if ((isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v)) || softfloat_exceptionFlags)
+  WRITE_FRD(f64(defaultNaNF64UI));
 set_fp_exceptions;