Implement new FP encoding

[riscv-isa-sim.git] / riscv / insns / fmin_s.h

diff --git a/riscv/insns/fmin_s.h b/riscv/insns/fmin_s.h
index 831a7a255fed3fb8fd32083554a2255579221877..b813f45d7440cb638470e7b0f3a2e970156597bb 100644 (file)
--- a/riscv/insns/fmin_s.h
+++ b/riscv/insns/fmin_s.h
@@ -1,6 +1,6 @@
 require_extension('F');
 require_fp;
-WRITE_FRD(f32_lt_quiet(f32(FRS1), f32(FRS2)) || isNaNF32UI(FRS2) ? FRS1 : FRS2);
-if ((isNaNF32UI(FRS1) && isNaNF32UI(FRS2)) || softfloat_exceptionFlags)
-  WRITE_FRD(defaultNaNF32UI);
+WRITE_FRD(f32_lt_quiet(f32(FRS1), f32(FRS2)) || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
+if ((isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v)) || softfloat_exceptionFlags)
+  WRITE_FRD(f32(defaultNaNF32UI));
 set_fp_exceptions;