Implement new FP encoding

[riscv-isa-sim.git] / riscv / insns / fmul_d.h

diff --git a/riscv/insns/fmul_d.h b/riscv/insns/fmul_d.h
index a8adedd1bc17563aee013aef3f4bc76a0827b14f..9189d8d9ed4ffad7f9aff7dbc7f939076b092274 100644 (file)
--- a/riscv/insns/fmul_d.h
+++ b/riscv/insns/fmul_d.h
@@ -1,4 +1,5 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mul(FRS1, FRS2);
+WRITE_FRD(f64_mul(f64(FRS1), f64(FRS2)));
 set_fp_exceptions;