Implement new FP encoding

[riscv-isa-sim.git] / riscv / insns / fnmadd_d.h

diff --git a/riscv/insns/fnmadd_d.h b/riscv/insns/fnmadd_d.h
index 9529aebe46b0cdc35e4e615ba8accbb61b8828cc..e8dd743233cdf7ff7ef6dcc07231c003b8b98eb2 100644 (file)
--- a/riscv/insns/fnmadd_d.h
+++ b/riscv/insns/fnmadd_d.h
@@ -1,4 +1,5 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3 ^ (uint64_t)INT64_MIN);
+WRITE_FRD(f64_mulAdd(f64(f64(FRS1).v ^ F64_SIGN), f64(FRS2), f64(f64(FRS3).v ^ F64_SIGN)));
 set_fp_exceptions;