Implement new FP encoding

[riscv-isa-sim.git] / riscv / insns / fnmsub_d.h

diff --git a/riscv/insns/fnmsub_d.h b/riscv/insns/fnmsub_d.h
index ee74cab2724ee190fb91b7ab58a9fc113f601233..c29a0b93ca059d7dc74cfc7e399185941bf59ecc 100644 (file)
--- a/riscv/insns/fnmsub_d.h
+++ b/riscv/insns/fnmsub_d.h
@@ -1,5 +1,5 @@
 require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_mulAdd(f64(FRS1 ^ (uint64_t)INT64_MIN), f64(FRS2), f64(FRS3)).v);
+WRITE_FRD(f64_mulAdd(f64(f64(FRS1).v ^ F64_SIGN), f64(FRS2), f64(FRS3)));
 set_fp_exceptions;