Set badvaddr on instruction page faults

[riscv-isa-sim.git] / riscv / mmu.cc

diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index 4675f75f61734963054980c6c2c8efa448ff289b..92cb6dee955003559f9c705c6b5633661c895400 100644 (file)
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -45,8 +45,7 @@ void* mmu_t::refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch)
   if(unlikely((pte_perm & perm) != perm))
   {
     if (fetch)
-      throw trap_instruction_access_fault();
-
+      throw trap_instruction_access_fault(addr);
     if (store)
       throw trap_store_access_fault(addr);
     throw trap_load_access_fault(addr);