Set badvaddr on instruction page faults

[riscv-isa-sim.git] / riscv / trap.h

diff --git a/riscv/trap.h b/riscv/trap.h
index b79594885fdc06e0396c9e72763c8cf14308c25d..53df4f4033f0fc4e9d2efc17a404aea6e2760c12 100644 (file)
--- a/riscv/trap.h
+++ b/riscv/trap.h
@@ -42,8 +42,8 @@ class mem_trap_t : public trap_t
   const char* name() { return "trap_"#x; } \
 };
 
-DECLARE_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned)
-DECLARE_TRAP(CAUSE_FAULT_FETCH, instruction_access_fault)
+DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned)
+DECLARE_MEM_TRAP(CAUSE_FAULT_FETCH, instruction_access_fault)
 DECLARE_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction)
 DECLARE_TRAP(CAUSE_PRIVILEGED_INSTRUCTION, privileged_instruction)
 DECLARE_TRAP(CAUSE_FP_DISABLED, fp_disabled)