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Exceptions in Debug Mode, stay in Debug Mode.
[riscv-isa-sim.git]
/
riscv
/
gdbserver.cc
2016-05-23
Tim Newsome
Exceptions in Debug Mode, stay in Debug Mode.
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2016-05-23
Tim Newsome
Read FP registers, and general CSRs*
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2016-05-23
Tim Newsome
Continue works well enough for DebugTest.test_exit
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2016-05-23
Tim Newsome
Refactor how we track in-progress operations.
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2016-05-23
Tim Newsome
gdb can attach and read the PC:
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2016-05-23
Tim Newsome
processor_t unfriends gdbserver_t.
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2016-05-23
Tim Newsome
Correctly read PC on halt.
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2016-05-23
Tim Newsome
Fix store to clear debug interrupt.
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2016-05-23
Tim Newsome
Add debug_module bus device.
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2016-05-23
Tim Newsome
ROM -> RAM -> ROM, waiting for debug int.
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2016-05-23
Tim Newsome
When gdb connects, jump to Debug ROM and segfault.
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2016-05-23
Tim Newsome
Gutting direct-access gdb.
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2016-05-23
Tim Newsome
Add --gdb-port
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2016-05-23
Tim Newsome
Minor cleanup.
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2016-05-23
Tim Newsome
Update regnum handling to match gdb CSR changes.
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2016-05-23
Tim Newsome
Implement register writes.
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2016-05-23
Tim Newsome
Implement reading of CSRs.
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2016-05-23
Tim Newsome
Add some tests that pass and test something.
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2016-05-23
Tim Newsome
Flush icache when using swbps and report to gdb.
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2016-05-23
Tim Newsome
Software breakpoints seem to work.
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2016-05-23
Tim Newsome
Rewrite GPL'd code from OpenOCD.
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2016-05-23
Tim Newsome
Looks like single step works.
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2016-05-23
Tim Newsome
Add -H to start halted.
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2016-05-23
Tim Newsome
Implement binary memory write.
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2016-05-23
Tim Newsome
Now you can halt/continue from gdb.
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2016-05-23
Tim Newsome
Register read looks sane now.
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2016-05-23
Tim Newsome
gdb can now read spike memory.
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2016-05-23
Tim Newsome
Hack to the point where gdb reads a register.
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2016-05-23
Tim Newsome
Listen on a socket for gdb to connect to.
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