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Save/restore tselect. Set dmode.
[riscv-isa-sim.git]
/
riscv
/
gdbserver.h
2016-08-31
Tim Newsome
Save/restore tselect. Set dmode.
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2016-08-22
Tim Newsome
Implement address and data triggers.
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2016-07-28
Tim Newsome
Add support for virtual priv register. (#59)
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2016-06-28
Tim Newsome
Make gdbserver code work with small Debug RAM.
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2016-06-28
Tim Newsome
Support debugging 32-bit spike instances.
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2016-05-23
Tim Newsome
Exceptions in Debug Mode don't update any regs.
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2016-05-23
Tim Newsome
Make sure to fence.i after setting/clearing a swbp
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2016-05-23
Tim Newsome
Single step appears to work.
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2016-05-23
Tim Newsome
Software breakpoints sort of work.
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2016-05-23
Tim Newsome
Walk page tables to translate addresses.
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2016-05-23
Tim Newsome
Turn operation into a queue,
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2016-05-23
Tim Newsome
Save/restore mstatus, too.
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2016-05-23
Tim Newsome
Properly save/restore dpc, mcause, mbadaddr.
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2016-05-23
Tim Newsome
Refactor how we track in-progress operations.
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2016-05-23
Tim Newsome
gdb can attach and read the PC:
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2016-05-23
Tim Newsome
Fix store to clear debug interrupt.
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2016-05-23
Tim Newsome
Add debug_module bus device.
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2016-05-23
Tim Newsome
ROM -> RAM -> ROM, waiting for debug int.
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2016-05-23
Tim Newsome
Only halt on ebreak if a debugger is attached.
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2016-05-23
Tim Newsome
Add --gdb-port
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2016-05-23
Tim Newsome
Implement register writes.
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2016-05-23
Tim Newsome
Flush icache when using swbps and report to gdb.
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2016-05-23
Tim Newsome
Software breakpoints seem to work.
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2016-05-23
Tim Newsome
Looks like single step works.
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2016-05-23
Tim Newsome
Implement binary memory write.
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2016-05-23
Tim Newsome
Now you can halt/continue from gdb.
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2016-05-23
Tim Newsome
Register read looks sane now.
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2016-05-23
Tim Newsome
gdb can now read spike memory.
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2016-05-23
Tim Newsome
Hack to the point where gdb reads a register.
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2016-05-23
Tim Newsome
Listen on a socket for gdb to connect to.
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