Single step appears to work.
[riscv-isa-sim.git] / riscv / gdbserver.h
2016-05-23 Tim NewsomeSingle step appears to work.
2016-05-23 Tim NewsomeSoftware breakpoints sort of work.
2016-05-23 Tim NewsomeWalk page tables to translate addresses.
2016-05-23 Tim NewsomeTurn operation into a queue,
2016-05-23 Tim NewsomeSave/restore mstatus, too.
2016-05-23 Tim NewsomeProperly save/restore dpc, mcause, mbadaddr.
2016-05-23 Tim NewsomeRefactor how we track in-progress operations.
2016-05-23 Tim Newsomegdb can attach and read the PC:
2016-05-23 Tim NewsomeFix store to clear debug interrupt.
2016-05-23 Tim NewsomeAdd debug_module bus device.
2016-05-23 Tim NewsomeROM -> RAM -> ROM, waiting for debug int.
2016-05-23 Tim NewsomeOnly halt on ebreak if a debugger is attached.
2016-05-23 Tim NewsomeAdd --gdb-port
2016-05-23 Tim NewsomeImplement register writes.
2016-05-23 Tim NewsomeFlush icache when using swbps and report to gdb.
2016-05-23 Tim NewsomeSoftware breakpoints seem to work.
2016-05-23 Tim NewsomeLooks like single step works.
2016-05-23 Tim NewsomeImplement binary memory write.
2016-05-23 Tim NewsomeNow you can halt/continue from gdb.
2016-05-23 Tim NewsomeRegister read looks sane now.
2016-05-23 Tim Newsomegdb can now read spike memory.
2016-05-23 Tim NewsomeHack to the point where gdb reads a register.
2016-05-23 Tim NewsomeListen on a socket for gdb to connect to.