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Refactor and fix LR/SC implementation (#217)
[riscv-isa-sim.git]
/
riscv
/
sim.cc
2011-05-01
Andrew Waterman
[sim] hacked in a dcache simulator
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2011-04-17
Andrew Waterman
[sim] added "str" debug command
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2011-04-15
Andrew Waterman
[sim] added icache simulator (disabled by default)
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2011-04-10
Yunsup Lee
[sim] add vt stuff
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2011-03-25
Andrew Waterman
[xcc,pk,opcodes,sim] updated encoding/insn names
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2011-01-19
Andrew Waterman
[opcodes, sim, xcc] made *w insns illegal in RV32
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2010-12-27
Andrew Waterman
[sim] fixed some compiler warnings
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2010-11-22
Andrew Waterman
[xcc, sim, pk] link register is now x1
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2010-09-09
Andrew Waterman
Merge branch 'master' of /project/eecs/parlab/git/proje...
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2010-09-08
Yunsup Lee
[sim] add while to interactive_until
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2010-09-08
Yunsup Lee
[sim] change applink for tohost/fromhost
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2010-09-07
Andrew Waterman
[sim] fixed bug in msub.d; added ability to print FPRs...
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2010-08-10
Andrew Waterman
[sim] removed unused elf loader
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2010-07-23
Yunsup Lee
[sim] various fixes to get the sim work with the fesvr
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2010-07-22
Andrew Waterman
[pk,sim] first cut of appserver communication link
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2010-07-19
Andrew Waterman
Reorganized directory structure
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