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2021-04-10	Cesar Strauss	Add 1<<r3 test cases to TestIssuer	commit \| commitdiff \| tree
2021-04-10	Cesar Strauss	Add test cases for 1<<r3 predication	commit \| commitdiff \| tree
2021-04-06	Cesar Strauss	Make the VL loop reentrant in HDL	commit \| commitdiff \| tree
2021-04-06	Cesar Strauss	Add a HDL test case, where we start at the middle of...	commit \| commitdiff \| tree
2021-04-06	Cesar Strauss	Start the test case from a point where the predicate...	commit \| commitdiff \| tree
2021-04-04	Cesar Strauss	Add test case for reentrant VL loop	commit \| commitdiff \| tree
2021-04-03	Cesar Strauss	Reminder for a possible hardware optimization	commit \| commitdiff \| tree
2021-04-03	Cesar Strauss	Be more precise when using a one-bit constant	commit \| commitdiff \| tree
2021-04-03	Cesar Strauss	Fix typo	commit \| commitdiff \| tree
2021-04-03	Cesar Strauss	Add test case with all mask bits equal to zero	commit \| commitdiff \| tree
2021-04-03	Cesar Strauss	Add a test case for integer single predication	commit \| commitdiff \| tree
2021-04-03	Cesar Strauss	Disallow unknown encmodes in SVP64 Assembly	commit \| commitdiff \| tree
2021-04-03	Cesar Strauss	Enable remaining disabled test cases	commit \| commitdiff \| tree
2021-04-03	Cesar Strauss	Allow the Simulator to handle back-to-back signaling...	commit \| commitdiff \| tree
2021-04-03	Cesar Strauss	Signal the simulator when completing a VL loop	commit \| commitdiff \| tree
2021-04-03	Cesar Strauss	Fix typo	commit \| commitdiff \| tree
2021-04-03	Cesar Strauss	Add twin predication test	commit \| commitdiff \| tree
2021-04-02	Cesar Strauss	End VL loop as soon as either src/dst step reaches VL	commit \| commitdiff \| tree
2021-04-02	Cesar Strauss	Fix typo	commit \| commitdiff \| tree
2021-04-02	Cesar Strauss	Add VEXPAND test case for the ISA Simulator	commit \| commitdiff \| tree
2021-04-02	Cesar Strauss	Add VCOMPRESS test case for the ISA Simulator	commit \| commitdiff \| tree
2021-04-02	Cesar Strauss	Put sanity check inside the existing '2Pred' case,...	commit \| commitdiff \| tree
2021-04-02	Cesar Strauss	Enforce explicit src/dest masks on CR twin-predication	commit \| commitdiff \| tree
2021-04-02	Cesar Strauss	Disallow mixing of sm=xx and/or dm=xx with m=xx on...	commit \| commitdiff \| tree
2021-04-02	Cesar Strauss	Disallow dm=xx on single predication	commit \| commitdiff \| tree
2021-04-02	Cesar Strauss	Fix typo	commit \| commitdiff \| tree
2021-04-02	Cesar Strauss	Really enforce sm=xx not being allowed on single-pred	commit \| commitdiff \| tree
2021-04-02	Cesar Strauss	Keep mask mode flags separate	commit \| commitdiff \| tree
2021-03-30	Cesar Strauss	Enable VCOMPRESS test case	commit \| commitdiff \| tree
2021-03-30	Cesar Strauss	Add new twin predication case	commit \| commitdiff \| tree
2021-03-30	Cesar Strauss	Adjust twin predication cases for the new syntax	commit \| commitdiff \| tree
2021-03-30	Cesar Strauss	Skip leading zero bits on predicate masks	commit \| commitdiff \| tree
2021-03-30	Cesar Strauss	Memory port seems to have been renamed	commit \| commitdiff \| tree
2021-03-28	Cesar Strauss	Move DECODE_SV to its place between MASK_WAIT and INSN_EXECUTE	commit \| commitdiff \| tree
2021-03-28	Cesar Strauss	Move instruction decoding to after predication	commit \| commitdiff \| tree
2021-03-28	Cesar Strauss	Prepare to advance src/dst step after getting the predicate...	commit \| commitdiff \| tree
2021-03-22	Cesar Strauss	Add test cases for integer VCOMPRESS and VEXPAND	commit \| commitdiff \| tree
2021-03-22	Cesar Strauss	Skip fetching integer predicate mask when register...	commit \| commitdiff \| tree
2021-03-22	Cesar Strauss	Add traces for the new FSM and integer predicate decoding	commit \| commitdiff \| tree
2021-03-22	Cesar Strauss	Decode and fetch integer predicate registers	commit \| commitdiff \| tree
2021-03-21	Cesar Strauss	Fix typo	commit \| commitdiff \| tree
2021-03-21	Cesar Strauss	Add unique name to decoded predication signals	commit \| commitdiff \| tree
2021-03-21	Cesar Strauss	Revert removal of *.value from Enums	commit \| commitdiff \| tree
2021-03-21	Cesar Strauss	Fix syntax	commit \| commitdiff \| tree
2021-03-21	Cesar Strauss	Start work on the predicate fetch FSM	commit \| commitdiff \| tree
2021-03-21	Cesar Strauss	Add predication test case, initially disabled	commit \| commitdiff \| tree
2021-03-16	Cesar Strauss	Use symbolic values for subfields and bits	commit \| commitdiff \| tree
2021-03-16	Cesar Strauss	Add subfield and bit definitions for the SVP64 RM mode...	commit \| commitdiff \| tree
2021-03-16	Cesar Strauss	Define and initialise the mode variable, to be used...	commit \| commitdiff \| tree
2021-03-16	Cesar Strauss	Rename class so it does not clash with the enum	commit \| commitdiff \| tree
2021-03-15	Cesar Strauss	Fix import	commit \| commitdiff \| tree
2021-03-14	Cesar Strauss	Activate the VL==0 loop with any SVP64 prefix whatsoever	commit \| commitdiff \| tree
2021-03-11	Cesar Strauss	Bring a few test cases from test_caller_64.py	commit \| commitdiff \| tree
2021-03-11	Cesar Strauss	Test case for two successive SV instructions	commit \| commitdiff \| tree
2021-03-09	Cesar Strauss	Enable VL==0 vector instruction skip test case	commit \| commitdiff \| tree
2021-03-09	Cesar Strauss	Add some extra debug traces to the GTKWave document	commit \| commitdiff \| tree
2021-03-09	Cesar Strauss	Create a new signal for the Simulator to wait on	commit \| commitdiff \| tree
2021-03-08	Cesar Strauss	Remove the unused internal insn_done signal	commit \| commitdiff \| tree
2021-03-08	Cesar Strauss	Fix argument order to match function declaration	commit \| commitdiff \| tree
2021-03-07	Cesar Strauss	Fix missing NIA update on ISACaller	commit \| commitdiff \| tree
2021-03-07	Cesar Strauss	Merge WAIT_RESET into INSN_FETCH on the Issue FSM	commit \| commitdiff \| tree
2021-03-07	Cesar Strauss	Implement the VL==0 loop	commit \| commitdiff \| tree
2021-03-06	Cesar Strauss	Allow updating the PC and SVSTATE registers while stopped	commit \| commitdiff \| tree
2021-03-06	Cesar Strauss	Enable the Simple-V loop test case	commit \| commitdiff \| tree
2021-03-06	Cesar Strauss	Begin to implement the Simple-V loop	commit \| commitdiff \| tree
2021-03-06	Cesar Strauss	Do not reset pc_changed and sv_changed at instruction end	commit \| commitdiff \| tree
2021-03-06	Cesar Strauss	Make the raw opcode input port of the decoder stay...	commit \| commitdiff \| tree
2021-03-05	Cesar Strauss	Move writing of the PC state register to the issue FSM	commit \| commitdiff \| tree
2021-03-05	Cesar Strauss	Move the wait on "core stop" out of fetch, and into...	commit \| commitdiff \| tree
2021-02-27	Cesar Strauss	Add traces for the new FSM	commit \| commitdiff \| tree
2021-02-26	Cesar Strauss	Add a vector case with VL == 0	commit \| commitdiff \| tree
2021-02-26	Cesar Strauss	Implement a decode/issue FSM between fetch and execute	commit \| commitdiff \| tree
2021-02-22	Cesar Strauss	Fix typo when calculating PowerDecoder2.no_out_vec	commit \| commitdiff \| tree
2021-02-21	Cesar Strauss	The field selection function was moved to nmutil.util	commit \| commitdiff \| tree
2021-02-21	Cesar Strauss	Hide the register augmentation traces by default	commit \| commitdiff \| tree
2021-02-21	Cesar Strauss	The new version of "sel" is smart enough to find a...	commit \| commitdiff \| tree
2021-02-21	Cesar Strauss	Use the new selection field function from nmutil	commit \| commitdiff \| tree
2021-02-21	Cesar Strauss	Use symbolic values as field sizes	commit \| commitdiff \| tree
2021-02-21	Cesar Strauss	Replace all hardcoded shifts into RM by usage of SVP64RMFields	commit \| commitdiff \| tree
2021-02-20	Cesar Strauss	Actually forward the field width to field_slice()	commit \| commitdiff \| tree
2021-02-20	Cesar Strauss	Assemble the SV64 prefix from its subfields using SVP64Prefi...	commit \| commitdiff \| tree
2021-02-20	Cesar Strauss	Fix more MSB0 issues in comments	commit \| commitdiff \| tree
2021-02-20	Cesar Strauss	Replace more hardcoded constants with symbolic field...	commit \| commitdiff \| tree
2021-02-17	Cesar Strauss	Use subfield bit selection to extract the RM SVP64...	commit \| commitdiff \| tree
2021-02-17	Cesar Strauss	Replace MSB-i by symbolic subfield indices and selectors	commit \| commitdiff \| tree
2021-02-17	Cesar Strauss	Add the SVSTATE traces to GTKWave to allow debugging...	commit \| commitdiff \| tree
2021-02-17	Cesar Strauss	Initialize the core SVSTATE from the corresponding...	commit \| commitdiff \| tree
2021-02-17	Cesar Strauss	Revert "Setup SVSTATE, from the test settings, at the...	commit \| commitdiff \| tree
2021-02-17	Cesar Strauss	Add a function to select bits from a signal into a...	commit \| commitdiff \| tree
2021-02-17	Cesar Strauss	Add a case for checking the EXTRA field and register...	commit \| commitdiff \| tree
2021-02-17	Cesar Strauss	Add traces to debug SVP64 prefix decoding issues	commit \| commitdiff \| tree
2021-02-17	Cesar Strauss	Setup SVSTATE, from the test settings, at the start	commit \| commitdiff \| tree
2021-02-16	Cesar Strauss	Fix MSB0 issues for SVP64	commit \| commitdiff \| tree
2021-02-15	Cesar Strauss	Simplify obtaining the PC from the register file	commit \| commitdiff \| tree
2021-02-14	Cesar Strauss	Show traces for the register numbers of the current...	commit \| commitdiff \| tree
2021-02-14	Cesar Strauss	Fix width of the "extra" input on the Extra decoder	commit \| commitdiff \| tree
2021-02-14	Cesar Strauss	Fix conversion to MSB0	commit \| commitdiff \| tree
2021-02-14	Cesar Strauss	Remove obsolete comment	commit \| commitdiff \| tree
2021-02-13	Cesar Strauss	Fetch and decode the SVP64 prefix	commit \| commitdiff \| tree
2021-02-13	Cesar Strauss	Check the PC value at the end of each instruction	commit \| commitdiff \| tree
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