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more openpower import conversion
2021-04-23 Luke Kenneth Casson... more openpower import conversion
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2021-04-23 Luke Kenneth Casson... move over to from openpower imports
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2021-04-23 Luke Kenneth Casson... move over to openpower-isa repo
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2021-04-23 Luke Kenneth Casson... move over to openpower-isa
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2021-04-23 Luke Kenneth Casson... moving more over to openpower-isa repo
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2021-04-23 Luke Kenneth Casson... removing more as moved over to openpower-isa
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2021-04-23 Luke Kenneth Casson... submodule update
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2021-04-22 Luke Kenneth Casson... add debugging and buffering to CacheRam
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2021-04-22 Luke Kenneth Casson... whitespace
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2021-04-22 Luke Kenneth Casson... r1.end_row_ix off-by-one in dcache
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2021-04-22 Luke Kenneth Casson... sync missing in dcache
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2021-04-22 Luke Kenneth Casson... dcache.py code-comments
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2021-04-22 Luke Kenneth Casson... cleanup dcache
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2021-04-22 Luke Kenneth Casson... error using sync, should have been comb
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2021-04-21 Luke Kenneth Casson... experimenting with dcache
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2021-04-20 Luke Kenneth Casson... add enable MMU option to issuer_verilog.py
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2021-04-20 Luke Kenneth Casson... cannot pass in arguments to Core - must be done with...
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2021-04-20 Luke Kenneth Casson... use soc.bus.sram instead of nmigen_soc.wishbone.sram
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2021-04-20 Luke Kenneth Casson... add wishbone sram.py (move from nmigen-soc)
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2021-04-19 Luke Kenneth Casson... give independent names to spblock512w64b8ws
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2021-04-18 Luke Kenneth Casson... give spblock512 a name as a submodule
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2021-04-18 Luke Kenneth Casson... create signal on test_issuer which gives PLL clk_sel_i...
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2021-04-18 Luke Kenneth Casson... rename SPBlock_512W64B8W to lowercase
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2021-04-18 Luke Kenneth Casson... submodule update
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2021-04-18 Luke Kenneth Casson... rename PLL pins to match LIP6.fr PLL
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2021-04-18 Luke Kenneth Casson... core_stopped_i unused: remove
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2021-04-18 Luke Kenneth Casson... submodule update
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2021-04-18 Luke Kenneth Casson... submodule update
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2021-04-18 Luke Kenneth Casson... add pypi upload to Makefile
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2021-04-18 Luke Kenneth Casson... add OS Independent classifier
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2021-04-18 Luke Kenneth Casson... update README
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2021-04-18 Luke Kenneth Casson... update setup.py to make it "safe" for uploading to...
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2021-04-17 Luke Kenneth Casson... experiment with alternative PID in radix mmu
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2021-04-17 Luke Kenneth Casson... pass in SPRs each time on radix test
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2021-04-17 Luke Kenneth Casson... add LD/ST radix unit test
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2021-04-16 Luke Kenneth Casson... submodule update
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2021-04-16 Luke Kenneth Casson... jtag utils, send tms before tck
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2021-04-16 Luke Kenneth Casson... sigh, new_shift wrong bitwidth
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2021-04-16 Luke Kenneth Casson... put mbits back into segment_check (like it is in microwatt)
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2021-04-16 Luke Kenneth Casson... radixmmu cleanup
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2021-04-16 Luke Kenneth Casson... call addrshift and get_pgtable_addr inside while loop...
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2021-04-16 Luke Kenneth Casson... code-cleanup in radixmmu
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2021-04-15 Luke Kenneth Casson... whitespace and corrections to NLS, RTS1, RTS2
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2021-04-15 Luke Kenneth Casson... concat en_sigs together in JTAG to make sure they are...
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2021-04-15 Luke Kenneth Casson... add icachemmu option to ISACaller
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2021-04-14 Luke Kenneth Casson... submodule update
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2021-04-14 Luke Kenneth Casson... whitespace
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2021-04-14 Luke Kenneth Casson... submodule update
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2021-04-09 Luke Kenneth Casson... add blinken lights assembly (not used yet)
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2021-04-09 Luke Kenneth Casson... test firmware upload program needed to branch back...
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2021-04-08 Luke Kenneth Casson... sort out pc reset when DMI interface requests reset
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2021-04-08 Luke Kenneth Casson... submodule update
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2021-04-08 Luke Kenneth Casson... argh, wb jtag stall probably is not working
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2021-04-08 Luke Kenneth Casson... upload over 32-bit JTAG Wishbone
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2021-04-08 Luke Kenneth Casson... shrink JTAG master bus to 32-bit (match with litex)
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2021-04-07 Luke Kenneth Casson... submodule update
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2021-04-06 Luke Kenneth Casson... 4k SRAM Instance needs write-enable @ 8-bit width
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2021-04-06 Luke Kenneth Casson... 8-bit granularity on JTAG wishbone
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2021-04-06 Luke Kenneth Casson... remove unneeded code
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2021-04-06 Luke Kenneth Casson... git submodule update
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2021-04-05 Luke Kenneth Casson... litex submodule update
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2021-04-05 Luke Kenneth Casson... submodule update
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2021-04-01 Luke Kenneth Casson... git submodule update
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2021-04-01 Luke Kenneth Casson... TWI enabled in JTAG boundary scan
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2021-04-01 Luke Kenneth Casson... git submodule update
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2021-04-01 Luke Kenneth Casson... reduce subset of functions to be created in JTAG boundary...
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2021-04-01 Luke Kenneth Casson... use OrderedDict to restore exact order from JSON file
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2021-04-01 Luke Kenneth Casson... add soc-cocotb-sim submodule
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2021-04-01 Luke Kenneth Casson... submodule update
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2021-04-01 Luke Kenneth Casson... bug in iverilog, segfaults due to empty case statement
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2021-04-01 Luke Kenneth Casson... add no pll ls180 build
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2021-03-31 Luke Kenneth Casson... submodule update
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2021-03-30 Luke Kenneth Casson... add comments
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2021-03-30 Luke Kenneth Casson... use PRTBL SPR in RADIXMMU
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2021-03-30 Luke Kenneth Casson... submodule update
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2021-03-30 Luke Kenneth Casson... add comments, correct load addresses
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2021-03-30 Luke Kenneth Casson... submodule update
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2021-03-30 Luke Kenneth Casson... might have RADIXMMU at least semi-working... maybe
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2021-03-30 Luke Kenneth Casson... use assertEqual in RADIXMMU unit test
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2021-03-30 Luke Kenneth Casson... skip 1-pred check if m= used in SVP64Asm
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2021-03-30 Luke Kenneth Casson... submodule update
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2021-03-30 Luke Kenneth Casson... use port name for INT regfile to match up with test_runner...
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2021-03-30 Luke Kenneth Casson... corrections to Makefile for building / not-building...
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2021-03-30 Luke Kenneth Casson... bit of munging of Makefile, new targets
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2021-03-30 Luke Kenneth Casson... whoops Makefile error
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2021-03-29 Luke Kenneth Casson... correct segment check (off by one in LE/BE convert
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2021-03-29 Luke Kenneth Casson... update submodule
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2021-03-29 Luke Kenneth Casson... sort out pywriter.py when run with no args
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2021-03-29 Luke Kenneth Casson... remove "install" from run_sim dependency in Makefile
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2021-03-28 Luke Kenneth Casson... svp64-enable passed through to PowerDecoderSubsets...
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2021-03-28 Luke Kenneth Casson... whoops spelling mistake in SPRreduced Enums
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2021-03-28 Luke Kenneth Casson... rather invasive reduction of SPR regfile size
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2021-03-28 Luke Kenneth Casson... add option to reduce number of regfile ports (get DFFs...
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2021-03-28 Luke Kenneth Casson... reduce number of regfile ports
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2021-03-28 Luke Kenneth Casson... reduce regfile port usage on non-svp64
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2021-03-24 Luke Kenneth Casson... comment about using PriorityEncoder
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2021-03-24 Luke Kenneth Casson... debug output
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2021-03-24 Luke Kenneth Casson... add comment skipping in pagereader.py
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2021-03-24 Luke Kenneth Casson... make svp64 isa caller unit tests more obvious
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2021-03-24 Luke Kenneth Casson... add option to stop writing isa all.py in pseudocode...
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