2021-01-24 |
Luke Kenneth Casson... | changing svp64 asm syntax to use / instead of . as...
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2021-01-23 |
Luke Kenneth Casson... | move sanity-checks, add mode into svp64_rm
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2021-01-23 |
Luke Kenneth Casson... | cleanup on aisle 3 - simplify sv_mode svp64
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2021-01-23 |
Luke Kenneth Casson... | check src/dest mask exist if zeroing, svp64
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2021-01-23 |
Luke Kenneth Casson... | add predicate-result svp64 decoding
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2021-01-23 |
Luke Kenneth Casson... | add svp64 saturation decoding
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2021-01-23 |
Luke Kenneth Casson... | start decoding modes in svp64
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2021-01-23 |
Luke Kenneth Casson... | and now for something completely different...
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2021-01-23 |
Luke Kenneth Casson... | add elwidth encoding svp64, add more debug-print
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2021-01-23 |
Luke Kenneth Casson... | add svp64 subvl encoding
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2021-01-23 |
Luke Kenneth Casson... | add in svp64 predicate mask encoding
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2021-01-23 |
Luke Kenneth Casson... | capture CR 3 and 5 bit sv encodings
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2021-01-23 |
Luke Kenneth Casson... | start decoding EXTRA2/3
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2021-01-23 |
Luke Kenneth Casson... | start decoding sv EXTRAs and identifying them
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2021-01-23 |
Luke Kenneth Casson... | start to read RM CSV files
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2021-01-23 |
Luke Kenneth Casson... | add beginnings of svp64 assembly translator
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2021-01-22 |
Luke Kenneth Casson... | add example on how to access regs list for cmp
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2020-12-28 |
Luke Kenneth Casson... | add CR1 to power_enums
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2020-12-12 |
Luke Kenneth Casson... | skip madd, not implemented
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2020-12-09 |
Luke Kenneth Casson... | update submodules
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2020-12-09 |
Luke Kenneth Casson... | update submodules
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2020-12-06 |
Luke Kenneth Casson... | attempt to split into two separate GPIO banks due to...
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2020-12-03 |
Luke Kenneth Casson... | put ls180 litex bus width back to 32 bit temporarily
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2020-12-03 |
Luke Kenneth Casson... | argh issue with yosys ABC
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2020-12-03 |
Luke Kenneth Casson... | add 3 more 4k SRAMs, change WB bus width to 64 in ls180...
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2020-11-22 |
Luke Kenneth Casson... | simplify litex-core wishbone interfaces
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2020-11-14 |
Luke Kenneth Casson... | sigh, direction wrong in IOtypes litex core
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2020-11-13 |
Luke Kenneth Casson... | reduce number of nc in ls180 to 24
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2020-11-13 |
Luke Kenneth Casson... | reduce clkcsel ls180 width (2 pins), rename pll_18...
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2020-11-13 |
Luke Kenneth Casson... | rename and add pll lock signal to ls180
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2020-11-13 |
Luke Kenneth Casson... | rename ls180 litex pll_48 output to pll_18
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2020-11-13 |
Luke Kenneth Casson... | add enable/disable arguments (not ideal but it works...
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2020-11-13 |
Luke Kenneth Casson... | remove io_in/out now it is not needed for niolib
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2020-11-10 |
Luke Kenneth Casson... | add build commands to Makefile for versa ecp5
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2020-11-10 |
Luke Kenneth Casson... | submodule update
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2020-11-10 |
Luke Kenneth Casson... | remove ClockSelect module, use DummyPLL
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2020-11-10 |
Luke Kenneth Casson... | add separate DummyPLL module, according to API discussed at
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2020-11-07 |
Luke Kenneth Casson... | update submodule
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2020-11-06 |
Luke Kenneth Casson... | sigh sorting out litex pin-connections to sdram
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2020-11-04 |
Luke Kenneth Casson... | move back to 3.3v on X3 VERSA ECP5 connector
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2020-11-03 |
Luke Kenneth Casson... | swap jtag pinorder to match ulx3s
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2020-11-03 |
Luke Kenneth Casson... | change LVCMOS level on versa ecp5 jtag to 2.5v
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2020-10-30 |
Luke Kenneth Casson... | add JTAG extension to versa_ecp5 then we can use it
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2020-10-24 |
Luke Kenneth Casson... | submodule update
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2020-10-22 |
Luke Kenneth Casson... | add query about cross-domain on the JTAG enable of WB
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2020-10-22 |
Luke Kenneth Casson... | add detection and disable of Instruction Wishbone based...
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2020-10-22 |
Luke Kenneth Casson... | add detection and disable of LoadStore Wishbone based...
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2020-10-22 |
Luke Kenneth Casson... | add JTAG enable/disable of wishbone to TestIssuer
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2020-10-22 |
Luke Kenneth Casson... | add means to JTAG interface to enable/disable "stuff...
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2020-10-21 |
Luke Kenneth Casson... | fix up asserts (check correct pads/cores)
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2020-10-16 |
Luke Kenneth Casson... | experiment swapping dummy trap stage over to input
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2020-10-16 |
Luke Kenneth Casson... | re-enable tests
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2020-10-16 |
Luke Kenneth Casson... | manually run coresync clock for test issuer
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2020-10-16 |
Luke Kenneth Casson... | set defaults in pspec
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2020-10-16 |
Luke Kenneth Casson... | update submodule
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2020-10-16 |
Luke Kenneth Casson... | add extra (test dummy stage in trap to see if combinatorial...
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2020-10-16 |
Luke Kenneth Casson... | add LGPLv3+ notice and add copyright holders
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2020-10-15 |
Luke Kenneth Casson... | add commented-out connection to JTAG in ECP5 litex
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2020-10-15 |
Luke Kenneth Casson... | wrong pspec variable in selecting pll clock
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2020-10-15 |
Luke Kenneth Casson... | sorting out missing clock somewhere
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2020-10-15 |
Luke Kenneth Casson... | use "enable" and set default actions in getopt
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2020-10-15 |
Luke Kenneth Casson... | add extra variant to litex core
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2020-10-15 |
Luke Kenneth Casson... | syntax error
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2020-10-15 |
Luke Kenneth Casson... | disable gpio in litex core
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2020-10-15 |
Luke Kenneth Casson... | enable/disable litex irqs based on variant name
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2020-10-11 |
Luke Kenneth Casson... | add way to bypass PLL for ECP5 and sim
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2020-10-11 |
Luke Kenneth Casson... | comment out XICS/GPIO interrupt test, causes ECP5 litex...
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2020-10-11 |
Luke Kenneth Casson... | record commands for building ECP5
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2020-10-11 |
Luke Kenneth Casson... | litex sim.py operational
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2020-10-10 |
Luke Kenneth Casson... | add debug start/stop to firmware_upload script
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2020-10-10 |
Luke Kenneth Casson... | add DMI status / reset to firmware upload script
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2020-10-10 |
Luke Kenneth Casson... | add first version of firmware uploader
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2020-10-09 |
Luke Kenneth Casson... | use libresoc version of c4m-jtag repo
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2020-10-09 |
Luke Kenneth Casson... | submodule update
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2020-10-09 |
Luke Kenneth Casson... | drop in "undefined" function into ISAcaller namespace
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2020-10-09 |
Luke Kenneth Casson... | rename undef to undefined (preserving the fact that...
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2020-10-09 |
Luke Kenneth Casson... | missing yields in JTAG pads test to allow settling
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2020-10-08 |
Luke Kenneth Casson... | missing yields in JTAG pads test to allow settling
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2020-10-08 |
Luke Kenneth Casson... | minor icache cleanup
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2020-10-08 |
Luke Kenneth Casson... | add incoming PortInterface to be connected to LoadStoreCompUnit
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2020-10-08 |
Luke Kenneth Casson... | JTAG boundary scan test 1st attempt
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2020-10-08 |
Luke Kenneth Casson... | rework jtag test to use JTAG class not DMITAP
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2020-10-08 |
Luke Kenneth Casson... | split out jtag util functions to separate module
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2020-10-07 |
Luke Kenneth Casson... | missing invert_in field from shiftrot input record
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2020-10-07 |
Luke Kenneth Casson... | git submodule update
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2020-10-07 |
Luke Kenneth Casson... | reorder / reorganise reset signals slightly
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2020-10-06 |
Luke Kenneth Casson... | update comments on pimem.py
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2020-10-06 |
Luke Kenneth Casson... | comments
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2020-10-06 |
Luke Kenneth Casson... | add ports function to DummyPLL
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2020-10-06 |
Luke Kenneth Casson... | use pdecode2.do not pdecode2.e in test_pipe_caller...
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2020-10-06 |
Luke Kenneth Casson... | skip Decode2ToOperand from PowerDecodeSubset
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2020-10-06 |
Luke Kenneth Casson... | comment SRR1 mem.exception
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2020-10-06 |
Luke Kenneth Casson... | add SRR1 setting for LDST memory exception trap
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2020-10-06 |
Luke Kenneth Casson... | passing LDSTException over to Trap Pipeline
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2020-10-06 |
Luke Kenneth Casson... | add LDSTException decode/handling in PowerDecoder2
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2020-10-06 |
Luke Kenneth Casson... | make LDSTException fields added from list of fieldnames
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2020-10-06 |
Luke Kenneth Casson... | move LDSTException to mem_types
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2020-10-06 |
Luke Kenneth Casson... | submodule update
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2020-10-06 |
Luke Kenneth Casson... | add LDSTException to PortInterface
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2020-10-06 |
Luke Kenneth Casson... | add sdr bypass routing via JTAG boundary scan
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