riscv/debug_module.h

   1 // See LICENSE for license details.
   2 #ifndef _RISCV_DEBUG_MODULE_H
   3 #define _RISCV_DEBUG_MODULE_H
   4
   5 #include <set>
   6
   7 #include "devices.h"
   8
   9 class sim_t;
  10
  11 typedef struct {
  12   bool haltreq;
  13   bool resumereq;
  14   enum {
  15     HARTSTATUS_HALTED,
  16     HARTSTATUS_RUNNING,
  17     HARTSTATUS_UNAVAILABLE,
  18     HARTSTATUS_NOTEXIST
  19   } hartstatus;
  20   unsigned hartsel;
  21   bool hartreset;
  22   bool dmactive;
  23   bool reset;
  24   bool authenticated;
  25   bool authbusy;
  26   unsigned version;
  27 } dmcontrol_t;
  28
  29 typedef struct {
  30   bool autoexec7;
  31   bool autoexec6;
  32   bool autoexec5;
  33   bool autoexec4;
  34   bool autoexec3;
  35   bool autoexec2;
  36   bool autoexec1;
  37   bool autoexec0;
  38   enum {
  39     CMDERR_NONE = 0,
  40     CMDERR_BUSY = 1,
  41     CMDERR_NOTSUP = 2,
  42     CMDERR_EXCEPTION = 3,
  43     CMDERR_HALTRESUME = 4,
  44     CMDERR_OTHER = 7
  45   } cmderr;
  46   bool busy;
  47   unsigned datacount;
  48 } abstractcs_t;
  49
  50 class debug_module_data_t : public abstract_device_t
  51 {
  52   public:
  53     debug_module_data_t();
  54
  55     bool load(reg_t addr, size_t len, uint8_t* bytes);
  56     bool store(reg_t addr, size_t len, const uint8_t* bytes);
  57
  58     uint32_t read32(reg_t addr) const;
  59     void write32(reg_t addr, uint32_t value);
  60
  61     uint8_t data[DEBUG_EXCHANGE_SIZE];
  62 };
  63
  64 class debug_module_t : public abstract_device_t
  65 {
  66   public:
  67     debug_module_t(sim_t *sim);
  68
  69     void add_device(bus_t *bus);
  70
  71     bool load(reg_t addr, size_t len, uint8_t* bytes);
  72     bool store(reg_t addr, size_t len, const uint8_t* bytes);
  73
  74     // Debug Module Interface that the debugger (in our case through JTAG DTM)
  75     // uses to access the DM.
  76     // Return true for success, false for failure.
  77     bool dmi_read(unsigned address, uint32_t *value);
  78     bool dmi_write(unsigned address, uint32_t value);
  79
  80   private:
  81     static const unsigned progsize = 8;
  82
  83     sim_t *sim;
  84
  85     uint8_t debug_rom_entry[DEBUG_ROM_ENTRY_SIZE];
  86     uint8_t debug_rom_code[DEBUG_ROM_CODE_SIZE];
  87     uint8_t debug_rom_exception[DEBUG_ROM_EXCEPTION_SIZE];
  88     uint8_t program_buffer[progsize * 4];
  89     bool halted[1024];
  90     debug_module_data_t dmdata;
  91     // Instruction that will be placed at the current hart's ROM entry address
  92     // after the current action has completed.
  93     uint32_t next_action;
  94     bool action_executed;
  95
  96     void write32(uint8_t *rom, unsigned int index, uint32_t value);
  97     uint32_t read32(uint8_t *rom, unsigned int index);
  98
  99     dmcontrol_t dmcontrol;
 100     abstractcs_t abstractcs;
 101     uint32_t command;
 102
 103     processor_t *current_proc() const;
 104     void reset();
 105     bool perform_abstract_command();
 106 };
 107
 108 #endif