Improve debug performance.
[riscv-isa-sim.git] / riscv / jtag_dtm.h
1 #ifndef JTAG_DTM_H
2 #define JTAG_DTM_H
3
4 #include <stdint.h>
5
6 class debug_module_t;
7
8 typedef enum {
9 TEST_LOGIC_RESET,
10 RUN_TEST_IDLE,
11 SELECT_DR_SCAN,
12 CAPTURE_DR,
13 SHIFT_DR,
14 EXIT1_DR,
15 PAUSE_DR,
16 EXIT2_DR,
17 UPDATE_DR,
18 SELECT_IR_SCAN,
19 CAPTURE_IR,
20 SHIFT_IR,
21 EXIT1_IR,
22 PAUSE_IR,
23 EXIT2_IR,
24 UPDATE_IR
25 } jtag_state_t;
26
27 class jtag_dtm_t
28 {
29 static const unsigned idcode = 0xdeadbeef;
30
31 public:
32 jtag_dtm_t(debug_module_t *dm);
33 void reset();
34
35 void set_pins(bool tck, bool tms, bool tdi);
36
37 bool tdo() const { return _tdo; }
38
39 jtag_state_t state() const { return _state; }
40
41 private:
42 debug_module_t *dm;
43 bool _tck, _tms, _tdi, _tdo;
44 uint32_t ir;
45 const unsigned ir_length = 5;
46 uint64_t dr;
47 unsigned dr_length;
48
49 // abits must come before dtmcontrol so it can easily be used in the
50 // constructor.
51 const unsigned abits = 6;
52 uint32_t dtmcontrol;
53 uint64_t dmi;
54
55 jtag_state_t _state;
56
57 void capture_dr();
58 void update_dr();
59 };
60
61 #endif