riscv/mmu.cc

   1 // See LICENSE for license details.
   2
   3 #include "mmu.h"
   4 #include "sim.h"
   5 #include "processor.h"
   6
   7 mmu_t::mmu_t(char* _mem, size_t _memsz)
   8  : mem(_mem), memsz(_memsz), badvaddr(0),
   9    ptbr(0), sr(SR_S)
  10 {
  11   flush_tlb();
  12 }
  13
  14 mmu_t::~mmu_t()
  15 {
  16 }
  17
  18 void mmu_t::flush_icache()
  19 {
  20   memset(icache_tag, -1, sizeof(icache_tag));
  21 }
  22
  23 void mmu_t::flush_tlb()
  24 {
  25   memset(tlb_insn_tag, -1, sizeof(tlb_insn_tag));
  26   memset(tlb_load_tag, -1, sizeof(tlb_load_tag));
  27   memset(tlb_store_tag, -1, sizeof(tlb_store_tag));
  28
  29   flush_icache();
  30 }
  31
  32 reg_t mmu_t::refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch)
  33 {
  34   reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;
  35   reg_t expected_tag = addr & ~(PGSIZE-1);
  36
  37   reg_t pte = walk(addr);
  38
  39   reg_t pte_perm = pte & PTE_PERM;
  40   if (sr & SR_S) // shift supervisor permission bits into user perm bits
  41     pte_perm = (pte_perm/(PTE_SX/PTE_UX)) & PTE_PERM;
  42   pte_perm |= pte & PTE_E;
  43
  44   reg_t perm = (fetch ? PTE_UX : store ? PTE_UW : PTE_UR) | PTE_E;
  45   if(unlikely((pte_perm & perm) != perm))
  46   {
  47     if (fetch)
  48       throw trap_instruction_access_fault;
  49
  50     badvaddr = addr;
  51     throw store ? trap_store_access_fault : trap_load_access_fault;
  52   }
  53
  54   reg_t pgoff = addr & (PGSIZE-1);
  55   reg_t pgbase = pte >> PTE_PPN_SHIFT << PGSHIFT;
  56   reg_t paddr = pgbase + pgoff;
  57
  58   if (unlikely(tracer.interested_in_range(pgbase, pgbase + PGSIZE, store, fetch)))
  59     tracer.trace(paddr, bytes, store, fetch);
  60   else
  61   {
  62     tlb_load_tag[idx] = (pte_perm & PTE_UR) ? expected_tag : -1;
  63     tlb_store_tag[idx] = (pte_perm & PTE_UW) ? expected_tag : -1;
  64     tlb_insn_tag[idx] = (pte_perm & PTE_UX) ? expected_tag : -1;
  65     tlb_data[idx] = pgbase;
  66   }
  67
  68   return paddr;
  69 }
  70
  71 pte_t mmu_t::walk(reg_t addr)
  72 {
  73   pte_t pte = 0;
  74
  75   // the address must be a canonical sign-extended VA_BITS-bit number
  76   int shift = 8*sizeof(reg_t) - VA_BITS;
  77   if (((sreg_t)addr << shift >> shift) != (sreg_t)addr)
  78     ;
  79   else if (!(sr & SR_VM))
  80   {
  81     if(addr < memsz)
  82       pte = PTE_E | PTE_PERM | ((addr >> PGSHIFT) << PTE_PPN_SHIFT);
  83   }
  84   else
  85   {
  86     reg_t base = ptbr;
  87     reg_t ptd;
  88
  89     int ptshift = (LEVELS-1)*PTIDXBITS;
  90     for(reg_t i = 0; i < LEVELS; i++, ptshift -= PTIDXBITS)
  91     {
  92       reg_t idx = (addr >> (PGSHIFT+ptshift)) & ((1<<PTIDXBITS)-1);
  93
  94       reg_t pte_addr = base + idx*sizeof(pte_t);
  95       if(pte_addr >= memsz)
  96         break;
  97
  98       ptd = *(pte_t*)(mem+pte_addr);
  99       if(ptd & PTE_E)
 100       {
 101         // if this PTE is from a larger PT, fake a leaf
 102         // PTE so the TLB will work right
 103         reg_t vpn = addr >> PGSHIFT;
 104         ptd |= (vpn & ((1<<(ptshift))-1)) << PTE_PPN_SHIFT;
 105
 106         // fault if physical addr is invalid
 107         reg_t ppn = ptd >> PTE_PPN_SHIFT;
 108         if((ppn << PGSHIFT) + (addr & (PGSIZE-1)) < memsz)
 109           pte = ptd;
 110         break;
 111       }
 112       else if(!(ptd & PTE_T))
 113         break;
 114
 115       base = (ptd >> PTE_PPN_SHIFT) << PGSHIFT;
 116     }
 117   }
 118
 119   return pte;
 120 }
 121
 122 void mmu_t::register_memtracer(memtracer_t* t)
 123 {
 124   flush_tlb();
 125   tracer.hook(t);
 126 }