git.libre-soc.org Git - riscv-isa-sim.git/history

2013-03-26	Andrew Waterman	add BSD license	blob \| commitdiff \| raw
2013-03-26	Andrew Waterman	truncate effective addresses in rv32	blob \| commitdiff \| raw \| diff to current
2013-02-15	Andrew Waterman	don't store host pointers in soft TLB	blob \| commitdiff \| raw \| diff to current
2013-02-13	Andrew Waterman	clean up fetch-execute loop a bit	blob \| commitdiff \| raw \| diff to current
2013-02-13	Andrew Waterman	add I$/D$/L2$ simulators	blob \| commitdiff \| raw \| diff to current
2012-03-24	Andrew Waterman	new supervisor mode	blob \| commitdiff \| raw \| diff to current
2012-01-31	Andrew Waterman	don't set badvaddr for instruction access faults	blob \| commitdiff \| raw \| diff to current
2012-01-24	Andrew Waterman	check that virtual addresses are sign-extended	blob \| commitdiff \| raw \| diff to current
2011-11-01	Andrew Waterman	Fixed tight coupling of host and target page size	blob \| commitdiff \| raw \| diff to current
2011-06-20	Andrew Waterman	temporary undoing of renaming	blob \| commitdiff \| raw \| diff to current
2011-06-13	Andrew Waterman	[sim] renamed to riscv-isa-run	blob \| commitdiff \| raw
2011-06-12	Andrew Waterman	[xcc] tlb now stores host addresses	blob \| commitdiff \| raw \| diff to current
2011-06-11	Andrew Waterman	[xcc] cleaned up mmu code	blob \| commitdiff \| raw \| diff to current
2011-05-16	Andrew Waterman	[sim,pk] cleanups & initial virtual memory support	blob \| commitdiff \| raw \| diff to current

Simple-V augmented version of spike