riscv/mmu.cc

   1 // See LICENSE for license details.
   2
   3 #include "mmu.h"
   4 #include "sim.h"
   5 #include "processor.h"
   6
   7 mmu_t::mmu_t(char* _mem, size_t _memsz)
   8  : mem(_mem), memsz(_memsz), proc(NULL)
   9 {
  10   flush_tlb();
  11 }
  12
  13 mmu_t::~mmu_t()
  14 {
  15 }
  16
  17 void mmu_t::flush_icache()
  18 {
  19   for (size_t i = 0; i < ICACHE_ENTRIES; i++)
  20     icache[i].tag = -1;
  21 }
  22
  23 void mmu_t::flush_tlb()
  24 {
  25   memset(tlb_insn_tag, -1, sizeof(tlb_insn_tag));
  26   memset(tlb_load_tag, -1, sizeof(tlb_load_tag));
  27   memset(tlb_store_tag, -1, sizeof(tlb_store_tag));
  28
  29   flush_icache();
  30 }
  31
  32 reg_t mmu_t::translate(reg_t addr, access_type type)
  33 {
  34   if (!proc)
  35     return addr;
  36
  37   reg_t mode = proc->state.prv;
  38   if (type != FETCH && proc->state.prv == PRV_M &&
  39       get_field(proc->state.mstatus, MSTATUS_MPRV))
  40     mode = get_field(proc->state.mstatus, MSTATUS_MPP);
  41   if (get_field(proc->state.mstatus, MSTATUS_VM) == VM_MBARE)
  42     mode = PRV_M;
  43
  44   if (mode == PRV_M) {
  45     reg_t msb_mask = (reg_t(2) << (proc->xlen-1))-1; // zero-extend from xlen
  46     return addr & msb_mask;
  47   }
  48   return walk(addr, mode > PRV_U, type) | (addr & (PGSIZE-1));
  49 }
  50
  51 const uint16_t* mmu_t::fetch_slow_path(reg_t addr)
  52 {
  53   reg_t paddr = translate(addr, FETCH);
  54   if (paddr < memsz)
  55     refill_tlb(addr, paddr, FETCH);
  56   else
  57     throw trap_instruction_access_fault(addr);
  58   return (const uint16_t*)(mem + paddr);
  59 }
  60
  61 void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes)
  62 {
  63   reg_t paddr = translate(addr, LOAD);
  64   if (paddr < memsz) {
  65     memcpy(bytes, mem + paddr, len);
  66     if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD))
  67       tracer.trace(paddr, len, LOAD);
  68     else
  69       refill_tlb(addr, paddr, LOAD);
  70   } else if (!proc || !proc->sim->mmio_load(paddr, len, bytes)) {
  71     throw trap_load_access_fault(addr);
  72   }
  73 }
  74
  75 void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes)
  76 {
  77   reg_t paddr = translate(addr, STORE);
  78   if (paddr < memsz) {
  79     memcpy(mem + paddr, bytes, len);
  80     if (tracer.interested_in_range(paddr, paddr + PGSIZE, STORE))
  81       tracer.trace(paddr, len, STORE);
  82     else
  83       refill_tlb(addr, paddr, STORE);
  84   } else if (!proc || !proc->sim->mmio_store(paddr, len, bytes)) {
  85     throw trap_store_access_fault(addr);
  86   }
  87 }
  88
  89 void mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, access_type type)
  90 {
  91   reg_t idx = (vaddr >> PGSHIFT) % TLB_ENTRIES;
  92   reg_t expected_tag = vaddr >> PGSHIFT;
  93
  94   if (tlb_load_tag[idx] != expected_tag) tlb_load_tag[idx] = -1;
  95   if (tlb_store_tag[idx] != expected_tag) tlb_store_tag[idx] = -1;
  96   if (tlb_insn_tag[idx] != expected_tag) tlb_insn_tag[idx] = -1;
  97
  98   if (type == FETCH) tlb_insn_tag[idx] = expected_tag;
  99   else if (type == STORE) tlb_store_tag[idx] = expected_tag;
 100   else tlb_load_tag[idx] = expected_tag;
 101
 102   tlb_data[idx] = mem + paddr - vaddr;
 103 }
 104
 105 reg_t mmu_t::walk(reg_t addr, bool supervisor, access_type type)
 106 {
 107   int levels, ptidxbits, ptesize;
 108   switch (get_field(proc->get_state()->mstatus, MSTATUS_VM))
 109   {
 110     case VM_SV32: levels = 2; ptidxbits = 10; ptesize = 4; break;
 111     case VM_SV39: levels = 3; ptidxbits = 9; ptesize = 8; break;
 112     case VM_SV48: levels = 4; ptidxbits = 9; ptesize = 8; break;
 113     default: abort();
 114   }
 115
 116   // verify bits xlen-1:va_bits-1 are all equal
 117   int va_bits = PGSHIFT + levels * ptidxbits;
 118   reg_t mask = (reg_t(1) << (proc->xlen - (va_bits-1))) - 1;
 119   reg_t masked_msbs = (addr >> (va_bits-1)) & mask;
 120   if (masked_msbs != 0 && masked_msbs != mask)
 121     return -1;
 122
 123   reg_t base = proc->get_state()->sptbr << PGSHIFT;
 124   int ptshift = (levels - 1) * ptidxbits;
 125   for (int i = 0; i < levels; i++, ptshift -= ptidxbits) {
 126     reg_t idx = (addr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
 127
 128     // check that physical address of PTE is legal
 129     reg_t pte_addr = base + idx * ptesize;
 130     if (pte_addr >= memsz)
 131       break;
 132
 133     void* ppte = mem + pte_addr;
 134     reg_t pte = ptesize == 4 ? *(uint32_t*)ppte : *(uint64_t*)ppte;
 135     reg_t ppn = pte >> PTE_PPN_SHIFT;
 136
 137     if (PTE_TABLE(pte)) { // next level of page table
 138       base = ppn << PGSHIFT;
 139     } else if (!PTE_CHECK_PERM(pte, supervisor, type == STORE, type == FETCH)) {
 140       break;
 141     } else {
 142       // set referenced and possibly dirty bits.
 143       *(uint32_t*)ppte |= PTE_R | ((type == STORE) * PTE_D);
 144       // for superpage mappings, make a fake leaf PTE for the TLB's benefit.
 145       reg_t vpn = addr >> PGSHIFT;
 146       return (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
 147     }
 148   }
 149
 150   return -1;
 151 }
 152
 153 void mmu_t::register_memtracer(memtracer_t* t)
 154 {
 155   flush_tlb();
 156   tracer.hook(t);
 157 }