riscv/mmu.cc

   1 // See LICENSE for license details.
   2
   3 #include "mmu.h"
   4 #include "sim.h"
   5 #include "processor.h"
   6
   7 mmu_t::mmu_t(sim_t* sim, processor_t* proc)
   8  : sim(sim), proc(proc)
   9 {
  10   flush_tlb();
  11 }
  12
  13 mmu_t::~mmu_t()
  14 {
  15 }
  16
  17 void mmu_t::flush_icache()
  18 {
  19   for (size_t i = 0; i < ICACHE_ENTRIES; i++)
  20     icache[i].tag = -1;
  21 }
  22
  23 void mmu_t::flush_tlb()
  24 {
  25   memset(tlb_insn_tag, -1, sizeof(tlb_insn_tag));
  26   memset(tlb_load_tag, -1, sizeof(tlb_load_tag));
  27   memset(tlb_store_tag, -1, sizeof(tlb_store_tag));
  28
  29   flush_icache();
  30 }
  31
  32 reg_t mmu_t::translate(reg_t addr, access_type type)
  33 {
  34   if (!proc)
  35     return addr;
  36
  37   reg_t mode = proc->state.prv;
  38   bool pum = false;
  39   if (type != FETCH) {
  40     if (get_field(proc->state.mstatus, MSTATUS_MPRV))
  41       mode = get_field(proc->state.mstatus, MSTATUS_MPP);
  42     pum = (mode == PRV_S && get_field(proc->state.mstatus, MSTATUS_PUM));
  43   }
  44   if (get_field(proc->state.mstatus, MSTATUS_VM) == VM_MBARE)
  45     mode = PRV_M;
  46
  47   if (mode == PRV_M) {
  48     reg_t msb_mask = (reg_t(2) << (proc->xlen-1))-1; // zero-extend from xlen
  49     return addr & msb_mask;
  50   }
  51   return walk(addr, type, mode > PRV_U, pum) | (addr & (PGSIZE-1));
  52 }
  53
  54 const uint16_t* mmu_t::fetch_slow_path(reg_t vaddr)
  55 {
  56   reg_t paddr = translate(vaddr, FETCH);
  57
  58   // mmu_t::walk() returns -1 if it can't find a match. Of course -1 could also
  59   // be a valid address.
  60   if (paddr == ~(reg_t) 0 && vaddr != ~(reg_t) 0) {
  61     throw trap_instruction_access_fault(vaddr);
  62   }
  63
  64   if (sim->addr_is_mem(paddr)) {
  65     refill_tlb(vaddr, paddr, FETCH);
  66     return (const uint16_t*)sim->addr_to_mem(paddr);
  67   } else {
  68     if (!sim->mmio_load(paddr, sizeof fetch_temp, (uint8_t*)&fetch_temp))
  69       throw trap_instruction_access_fault(vaddr);
  70     return &fetch_temp;
  71   }
  72 }
  73
  74 void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes)
  75 {
  76   reg_t paddr = translate(addr, LOAD);
  77   if (sim->addr_is_mem(paddr)) {
  78     memcpy(bytes, sim->addr_to_mem(paddr), len);
  79     if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD))
  80       tracer.trace(paddr, len, LOAD);
  81     else
  82       refill_tlb(addr, paddr, LOAD);
  83   } else if (!sim->mmio_load(paddr, len, bytes)) {
  84     throw trap_load_access_fault(addr);
  85   }
  86 }
  87
  88 void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes)
  89 {
  90   reg_t paddr = translate(addr, STORE);
  91   if (sim->addr_is_mem(paddr)) {
  92     memcpy(sim->addr_to_mem(paddr), bytes, len);
  93     if (tracer.interested_in_range(paddr, paddr + PGSIZE, STORE))
  94       tracer.trace(paddr, len, STORE);
  95     else
  96       refill_tlb(addr, paddr, STORE);
  97   } else if (!sim->mmio_store(paddr, len, bytes)) {
  98     throw trap_store_access_fault(addr);
  99   }
 100 }
 101
 102 void mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, access_type type)
 103 {
 104   reg_t idx = (vaddr >> PGSHIFT) % TLB_ENTRIES;
 105   reg_t expected_tag = vaddr >> PGSHIFT;
 106
 107   if (tlb_load_tag[idx] != expected_tag) tlb_load_tag[idx] = -1;
 108   if (tlb_store_tag[idx] != expected_tag) tlb_store_tag[idx] = -1;
 109   if (tlb_insn_tag[idx] != expected_tag) tlb_insn_tag[idx] = -1;
 110
 111   if (type == FETCH) tlb_insn_tag[idx] = expected_tag;
 112   else if (type == STORE) tlb_store_tag[idx] = expected_tag;
 113   else tlb_load_tag[idx] = expected_tag;
 114
 115   tlb_data[idx] = sim->addr_to_mem(paddr) - vaddr;
 116 }
 117
 118 reg_t mmu_t::walk(reg_t addr, access_type type, bool supervisor, bool pum)
 119 {
 120   int levels, ptidxbits, ptesize;
 121   switch (get_field(proc->get_state()->mstatus, MSTATUS_VM))
 122   {
 123     case VM_SV32: levels = 2; ptidxbits = 10; ptesize = 4; break;
 124     case VM_SV39: levels = 3; ptidxbits = 9; ptesize = 8; break;
 125     case VM_SV48: levels = 4; ptidxbits = 9; ptesize = 8; break;
 126     default: abort();
 127   }
 128
 129   // verify bits xlen-1:va_bits-1 are all equal
 130   int va_bits = PGSHIFT + levels * ptidxbits;
 131   reg_t mask = (reg_t(1) << (proc->xlen - (va_bits-1))) - 1;
 132   reg_t masked_msbs = (addr >> (va_bits-1)) & mask;
 133   if (masked_msbs != 0 && masked_msbs != mask)
 134     return -1;
 135
 136   reg_t base = proc->get_state()->sptbr << PGSHIFT;
 137   int ptshift = (levels - 1) * ptidxbits;
 138   for (int i = 0; i < levels; i++, ptshift -= ptidxbits) {
 139     reg_t idx = (addr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
 140
 141     // check that physical address of PTE is legal
 142     reg_t pte_addr = base + idx * ptesize;
 143     if (!sim->addr_is_mem(pte_addr))
 144       break;
 145
 146     void* ppte = sim->addr_to_mem(pte_addr);
 147     reg_t pte = ptesize == 4 ? *(uint32_t*)ppte : *(uint64_t*)ppte;
 148     reg_t ppn = pte >> PTE_PPN_SHIFT;
 149
 150     if (PTE_TABLE(pte)) { // next level of page table
 151       base = ppn << PGSHIFT;
 152     } else if (pum && PTE_CHECK_PERM(pte, 0, type == STORE, type == FETCH)) {
 153       break;
 154     } else if (!PTE_CHECK_PERM(pte, supervisor, type == STORE, type == FETCH)) {
 155       break;
 156     } else {
 157       // set referenced and possibly dirty bits.
 158       *(uint32_t*)ppte |= PTE_R | ((type == STORE) * PTE_D);
 159       // for superpage mappings, make a fake leaf PTE for the TLB's benefit.
 160       reg_t vpn = addr >> PGSHIFT;
 161       reg_t value = (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
 162       return value;
 163     }
 164   }
 165
 166   return -1;
 167 }
 168
 169 void mmu_t::register_memtracer(memtracer_t* t)
 170 {
 171   flush_tlb();
 172   tracer.hook(t);
 173 }