riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  23         bool halt_on_reset)
  24   : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
  25   halt_on_reset(halt_on_reset)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31   disassembler = new disassembler_t(max_xlen);
  32
  33   reset();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87   isa |= 1L << ('u' - 'a'); // advertise support for user mode
  88
  89   while (*p) {
  90     isa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   // advertise support for supervisor and user modes
 110   isa |= 1L << ('s' - 'a');
 111   isa |= 1L << ('u' - 'a');
 112
 113   max_isa = isa;
 114 }
 115
 116 void state_t::reset()
 117 {
 118   memset(this, 0, sizeof(*this));
 119   prv = PRV_M;
 120   pc = DEFAULT_RSTVEC;
 121   load_reservation = -1;
 122   tselect = 0;
 123   for (unsigned int i = 0; i < num_triggers; i++)
 124     mcontrol[i].type = 2;
 125 }
 126
 127 void processor_t::set_debug(bool value)
 128 {
 129   debug = value;
 130   if (ext)
 131     ext->set_debug(value);
 132 }
 133
 134 void processor_t::set_histogram(bool value)
 135 {
 136   histogram_enabled = value;
 137 #ifndef RISCV_ENABLE_HISTOGRAM
 138   if (value) {
 139     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 140     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 141   }
 142 #endif
 143 }
 144
 145 void processor_t::reset()
 146 {
 147   state.reset();
 148   state.dcsr.halt = halt_on_reset;
 149   halt_on_reset = false;
 150   set_csr(CSR_MSTATUS, state.mstatus);
 151
 152   if (ext)
 153     ext->reset(); // reset the extension
 154 }
 155
 156 // Count number of contiguous 0 bits starting from the LSB.
 157 static int ctz(reg_t val)
 158 {
 159   int res = 0;
 160   if (val)
 161     while ((val & 1) == 0)
 162       val >>= 1, res++;
 163   return res;
 164 }
 165
 166 void processor_t::take_interrupt(reg_t pending_interrupts)
 167 {
 168   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 169   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 170   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 171
 172   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 173   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 174   if (enabled_interrupts == 0)
 175     enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
 176
 177   if (enabled_interrupts)
 178     throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
 179 }
 180
 181 static int xlen_to_uxl(int xlen)
 182 {
 183   if (xlen == 32)
 184     return 1;
 185   if (xlen == 64)
 186     return 2;
 187   abort();
 188 }
 189
 190 void processor_t::set_privilege(reg_t prv)
 191 {
 192   assert(prv <= PRV_M);
 193   if (prv == PRV_H)
 194     prv = PRV_U;
 195   mmu->flush_tlb();
 196   state.prv = prv;
 197 }
 198
 199 void processor_t::enter_debug_mode(uint8_t cause)
 200 {
 201   state.dcsr.cause = cause;
 202   state.dcsr.prv = state.prv;
 203   set_privilege(PRV_M);
 204   state.dpc = state.pc;
 205   state.pc = DEBUG_ROM_ENTRY;
 206 }
 207
 208 void processor_t::take_trap(trap_t& t, reg_t epc)
 209 {
 210   if (debug) {
 211     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 212             id, t.name(), epc);
 213     if (t.has_badaddr())
 214       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 215           t.get_badaddr());
 216   }
 217
 218   if (state.dcsr.cause) {
 219     if (t.cause() == CAUSE_BREAKPOINT) {
 220       state.pc = DEBUG_ROM_ENTRY;
 221     } else {
 222       state.pc = DEBUG_ROM_TVEC;
 223     }
 224     return;
 225   }
 226
 227   if (t.cause() == CAUSE_BREAKPOINT && (
 228               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 229               (state.prv == PRV_H && state.dcsr.ebreakh) ||
 230               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 231               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 232     enter_debug_mode(DCSR_CAUSE_SWBP);
 233     return;
 234   }
 235
 236   // by default, trap to M-mode, unless delegated to S-mode
 237   reg_t bit = t.cause();
 238   reg_t deleg = state.medeleg;
 239   bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0;
 240   if (interrupt)
 241     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 242   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 243     // handle the trap in S-mode
 244     state.pc = state.stvec;
 245     state.scause = t.cause();
 246     state.sepc = epc;
 247     if (t.has_badaddr())
 248       state.sbadaddr = t.get_badaddr();
 249
 250     reg_t s = state.mstatus;
 251     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
 252     s = set_field(s, MSTATUS_SPP, state.prv);
 253     s = set_field(s, MSTATUS_SIE, 0);
 254     set_csr(CSR_MSTATUS, s);
 255     set_privilege(PRV_S);
 256   } else {
 257     reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0;
 258     state.pc = (state.mtvec & ~(reg_t)1) + vector;
 259     state.mepc = epc;
 260     state.mcause = t.cause();
 261     if (t.has_badaddr())
 262       state.mbadaddr = t.get_badaddr();
 263
 264     reg_t s = state.mstatus;
 265     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
 266     s = set_field(s, MSTATUS_MPP, state.prv);
 267     s = set_field(s, MSTATUS_MIE, 0);
 268     set_csr(CSR_MSTATUS, s);
 269     set_privilege(PRV_M);
 270   }
 271
 272   yield_load_reservation();
 273 }
 274
 275 void processor_t::disasm(insn_t insn)
 276 {
 277   static uint64_t last_pc = 1, last_bits;
 278   static uint64_t executions = 1;
 279
 280   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 281   if (last_pc != state.pc || last_bits != bits) {
 282     if (executions != 1) {
 283       fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions);
 284     }
 285
 286     fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 287             id, state.pc, bits, disassembler->disassemble(insn).c_str());
 288     last_pc = state.pc;
 289     last_bits = bits;
 290     executions = 1;
 291   } else {
 292     executions++;
 293   }
 294 }
 295
 296 int processor_t::paddr_bits()
 297 {
 298   assert(xlen == max_xlen);
 299   return max_xlen == 64 ? 50 : 34;
 300 }
 301
 302 void processor_t::set_csr(int which, reg_t val)
 303 {
 304   val = zext_xlen(val);
 305   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 306   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 307   switch (which)
 308   {
 309     case CSR_FFLAGS:
 310       dirty_fp_state;
 311       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 312       break;
 313     case CSR_FRM:
 314       dirty_fp_state;
 315       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 316       break;
 317     case CSR_FCSR:
 318       dirty_fp_state;
 319       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 320       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 321       break;
 322     case CSR_MSTATUS: {
 323       if ((val ^ state.mstatus) &
 324           (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR))
 325         mmu->flush_tlb();
 326
 327       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 328                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
 329                  | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
 330                  | MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL |
 331                  (ext ? MSTATUS_XS : 0);
 332
 333       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 334
 335       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 336       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 337       if (max_xlen == 32)
 338         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 339       else
 340         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 341
 342       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 343       state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen));
 344       // U-XLEN == S-XLEN == M-XLEN
 345       xlen = max_xlen;
 346       break;
 347     }
 348     case CSR_MIP: {
 349       reg_t mask = MIP_SSIP | MIP_STIP;
 350       state.mip = (state.mip & ~mask) | (val & mask);
 351       break;
 352     }
 353     case CSR_MIE:
 354       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 355       break;
 356     case CSR_MIDELEG:
 357       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 358       break;
 359     case CSR_MEDELEG: {
 360       reg_t mask = 0;
 361 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 362 #include "encoding.h"
 363 #undef DECLARE_CAUSE
 364       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 365       break;
 366     }
 367     case CSR_MINSTRET:
 368     case CSR_MCYCLE:
 369       if (xlen == 32)
 370         state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
 371       else
 372         state.minstret = val;
 373       break;
 374     case CSR_MINSTRETH:
 375     case CSR_MCYCLEH:
 376       state.minstret = (val << 32) | (state.minstret << 32 >> 32);
 377       break;
 378     case CSR_SCOUNTEREN:
 379       state.scounteren = val;
 380       break;
 381     case CSR_MCOUNTEREN:
 382       state.mcounteren = val;
 383       break;
 384     case CSR_SSTATUS: {
 385       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 386                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR;
 387       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 388     }
 389     case CSR_SIP: {
 390       reg_t mask = MIP_SSIP & state.mideleg;
 391       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
 392     }
 393     case CSR_SIE:
 394       return set_csr(CSR_MIE,
 395                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 396     case CSR_SPTBR: {
 397       mmu->flush_tlb();
 398       if (max_xlen == 32)
 399         state.sptbr = val & (SPTBR32_PPN | SPTBR32_MODE);
 400       if (max_xlen == 64 && (get_field(val, SPTBR64_MODE) == SPTBR_MODE_OFF ||
 401                              get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV39 ||
 402                              get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV48))
 403         state.sptbr = val & (SPTBR64_PPN | SPTBR64_MODE);
 404       break;
 405     }
 406     case CSR_SEPC: state.sepc = val; break;
 407     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 408     case CSR_SSCRATCH: state.sscratch = val; break;
 409     case CSR_SCAUSE: state.scause = val; break;
 410     case CSR_SBADADDR: state.sbadaddr = val; break;
 411     case CSR_MEPC: state.mepc = val; break;
 412     case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break;
 413     case CSR_MSCRATCH: state.mscratch = val; break;
 414     case CSR_MCAUSE: state.mcause = val; break;
 415     case CSR_MBADADDR: state.mbadaddr = val; break;
 416     case CSR_MISA: {
 417       if (!(val & (1L << ('F' - 'A'))))
 418         val &= ~(1L << ('D' - 'A'));
 419
 420       // allow MAFDC bits in MISA to be modified
 421       reg_t mask = 0;
 422       mask |= 1L << ('M' - 'A');
 423       mask |= 1L << ('A' - 'A');
 424       mask |= 1L << ('F' - 'A');
 425       mask |= 1L << ('D' - 'A');
 426       mask |= 1L << ('C' - 'A');
 427       mask &= max_isa;
 428
 429       isa = (val & mask) | (isa & ~mask);
 430       break;
 431     }
 432     case CSR_TSELECT:
 433       if (val < state.num_triggers) {
 434         state.tselect = val;
 435       }
 436       break;
 437     case CSR_TDATA1:
 438       {
 439         mcontrol_t *mc = &state.mcontrol[state.tselect];
 440         if (mc->dmode && !state.dcsr.cause) {
 441           break;
 442         }
 443         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
 444         mc->select = get_field(val, MCONTROL_SELECT);
 445         mc->timing = get_field(val, MCONTROL_TIMING);
 446         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 447         mc->chain = get_field(val, MCONTROL_CHAIN);
 448         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 449         mc->m = get_field(val, MCONTROL_M);
 450         mc->h = get_field(val, MCONTROL_H);
 451         mc->s = get_field(val, MCONTROL_S);
 452         mc->u = get_field(val, MCONTROL_U);
 453         mc->execute = get_field(val, MCONTROL_EXECUTE);
 454         mc->store = get_field(val, MCONTROL_STORE);
 455         mc->load = get_field(val, MCONTROL_LOAD);
 456         // Assume we're here because of csrw.
 457         if (mc->execute)
 458           mc->timing = 0;
 459         trigger_updated();
 460       }
 461       break;
 462     case CSR_TDATA2:
 463       if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
 464         break;
 465       }
 466       if (state.tselect < state.num_triggers) {
 467         state.tdata2[state.tselect] = val;
 468       }
 469       break;
 470     case CSR_DCSR:
 471       state.dcsr.prv = get_field(val, DCSR_PRV);
 472       state.dcsr.step = get_field(val, DCSR_STEP);
 473       // TODO: ndreset and fullreset
 474       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 475       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 476       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 477       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 478       state.dcsr.halt = get_field(val, DCSR_HALT);
 479       break;
 480     case CSR_DPC:
 481       state.dpc = val;
 482       break;
 483     case CSR_DSCRATCH:
 484       state.dscratch = val;
 485       break;
 486   }
 487 }
 488
 489 reg_t processor_t::get_csr(int which)
 490 {
 491   uint32_t ctr_en = -1;
 492   if (state.prv < PRV_M)
 493     ctr_en &= state.mcounteren;
 494   if (state.prv < PRV_S)
 495     ctr_en &= state.scounteren;
 496   bool ctr_ok = (ctr_en >> (which & 31)) & 1;
 497
 498   if (ctr_ok) {
 499     if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
 500       return 0;
 501     if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
 502       return 0;
 503   }
 504   if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 505     return 0;
 506   if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H)
 507     return 0;
 508   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
 509     return 0;
 510
 511   switch (which)
 512   {
 513     case CSR_FFLAGS:
 514       require_fp;
 515       if (!supports_extension('F'))
 516         break;
 517       return state.fflags;
 518     case CSR_FRM:
 519       require_fp;
 520       if (!supports_extension('F'))
 521         break;
 522       return state.frm;
 523     case CSR_FCSR:
 524       require_fp;
 525       if (!supports_extension('F'))
 526         break;
 527       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 528     case CSR_INSTRET:
 529     case CSR_CYCLE:
 530       if (ctr_ok)
 531         return state.minstret;
 532       break;
 533     case CSR_MINSTRET:
 534     case CSR_MCYCLE:
 535       return state.minstret;
 536     case CSR_MINSTRETH:
 537     case CSR_MCYCLEH:
 538       if (xlen == 32)
 539         return state.minstret >> 32;
 540       break;
 541     case CSR_SCOUNTEREN: return state.scounteren;
 542     case CSR_MCOUNTEREN: return state.mcounteren;
 543     case CSR_SSTATUS: {
 544       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 545                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_UXL;
 546       reg_t sstatus = state.mstatus & mask;
 547       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 548           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 549         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 550       return sstatus;
 551     }
 552     case CSR_SIP: return state.mip & state.mideleg;
 553     case CSR_SIE: return state.mie & state.mideleg;
 554     case CSR_SEPC: return state.sepc;
 555     case CSR_SBADADDR: return state.sbadaddr;
 556     case CSR_STVEC: return state.stvec;
 557     case CSR_SCAUSE:
 558       if (max_xlen > xlen)
 559         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 560       return state.scause;
 561     case CSR_SPTBR:
 562       if (get_field(state.mstatus, MSTATUS_TVM))
 563         require_privilege(PRV_M);
 564       return state.sptbr;
 565     case CSR_SSCRATCH: return state.sscratch;
 566     case CSR_MSTATUS: return state.mstatus;
 567     case CSR_MIP: return state.mip;
 568     case CSR_MIE: return state.mie;
 569     case CSR_MEPC: return state.mepc;
 570     case CSR_MSCRATCH: return state.mscratch;
 571     case CSR_MCAUSE: return state.mcause;
 572     case CSR_MBADADDR: return state.mbadaddr;
 573     case CSR_MISA: return isa;
 574     case CSR_MARCHID: return 0;
 575     case CSR_MIMPID: return 0;
 576     case CSR_MVENDORID: return 0;
 577     case CSR_MHARTID: return id;
 578     case CSR_MTVEC: return state.mtvec;
 579     case CSR_MEDELEG: return state.medeleg;
 580     case CSR_MIDELEG: return state.mideleg;
 581     case CSR_TSELECT: return state.tselect;
 582     case CSR_TDATA1:
 583       if (state.tselect < state.num_triggers) {
 584         reg_t v = 0;
 585         mcontrol_t *mc = &state.mcontrol[state.tselect];
 586         v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 587         v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 588         v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 589         v = set_field(v, MCONTROL_SELECT, mc->select);
 590         v = set_field(v, MCONTROL_TIMING, mc->timing);
 591         v = set_field(v, MCONTROL_ACTION, mc->action);
 592         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 593         v = set_field(v, MCONTROL_MATCH, mc->match);
 594         v = set_field(v, MCONTROL_M, mc->m);
 595         v = set_field(v, MCONTROL_H, mc->h);
 596         v = set_field(v, MCONTROL_S, mc->s);
 597         v = set_field(v, MCONTROL_U, mc->u);
 598         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 599         v = set_field(v, MCONTROL_STORE, mc->store);
 600         v = set_field(v, MCONTROL_LOAD, mc->load);
 601         return v;
 602       } else {
 603         return 0;
 604       }
 605       break;
 606     case CSR_TDATA2:
 607       if (state.tselect < state.num_triggers) {
 608         return state.tdata2[state.tselect];
 609       } else {
 610         return 0;
 611       }
 612       break;
 613     case CSR_TDATA3: return 0;
 614     case CSR_DCSR:
 615       {
 616         uint32_t v = 0;
 617         v = set_field(v, DCSR_XDEBUGVER, 1);
 618         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 619         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 620         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 621         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 622         v = set_field(v, DCSR_STOPCYCLE, 0);
 623         v = set_field(v, DCSR_STOPTIME, 0);
 624         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 625         v = set_field(v, DCSR_STEP, state.dcsr.step);
 626         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 627         return v;
 628       }
 629     case CSR_DPC:
 630       return state.dpc;
 631     case CSR_DSCRATCH:
 632       return state.dscratch;
 633   }
 634   throw trap_illegal_instruction(0);
 635 }
 636
 637 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 638 {
 639   throw trap_illegal_instruction(0);
 640 }
 641
 642 insn_func_t processor_t::decode_insn(insn_t insn)
 643 {
 644   // look up opcode in hash table
 645   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 646   insn_desc_t desc = opcode_cache[idx];
 647
 648   if (unlikely(insn.bits() != desc.match)) {
 649     // fall back to linear search
 650     insn_desc_t* p = &instructions[0];
 651     while ((insn.bits() & p->mask) != p->match)
 652       p++;
 653     desc = *p;
 654
 655     if (p->mask != 0 && p > &instructions[0]) {
 656       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 657         // move to front of opcode list to reduce miss penalty
 658         while (--p >= &instructions[0])
 659           *(p+1) = *p;
 660         instructions[0] = desc;
 661       }
 662     }
 663
 664     opcode_cache[idx] = desc;
 665     opcode_cache[idx].match = insn.bits();
 666   }
 667
 668   return xlen == 64 ? desc.rv64 : desc.rv32;
 669 }
 670
 671 void processor_t::register_insn(insn_desc_t desc)
 672 {
 673   instructions.push_back(desc);
 674 }
 675
 676 void processor_t::build_opcode_map()
 677 {
 678   struct cmp {
 679     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 680       if (lhs.match == rhs.match)
 681         return lhs.mask > rhs.mask;
 682       return lhs.match > rhs.match;
 683     }
 684   };
 685   std::sort(instructions.begin(), instructions.end(), cmp());
 686
 687   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 688     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 689 }
 690
 691 void processor_t::register_extension(extension_t* x)
 692 {
 693   for (auto insn : x->get_instructions())
 694     register_insn(insn);
 695   build_opcode_map();
 696   for (auto disasm_insn : x->get_disasms())
 697     disassembler->add_insn(disasm_insn);
 698   if (ext != NULL)
 699     throw std::logic_error("only one extension may be registered");
 700   ext = x;
 701   x->set_processor(this);
 702 }
 703
 704 void processor_t::register_base_instructions()
 705 {
 706   #define DECLARE_INSN(name, match, mask) \
 707     insn_bits_t name##_match = (match), name##_mask = (mask);
 708   #include "encoding.h"
 709   #undef DECLARE_INSN
 710
 711   #define DEFINE_INSN(name) \
 712     REGISTER_INSN(this, name, name##_match, name##_mask)
 713   #include "insn_list.h"
 714   #undef DEFINE_INSN
 715
 716   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 717   build_opcode_map();
 718 }
 719
 720 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 721 {
 722   switch (addr)
 723   {
 724     case 0:
 725       if (len <= 4) {
 726         memset(bytes, 0, len);
 727         bytes[0] = get_field(state.mip, MIP_MSIP);
 728         return true;
 729       }
 730       break;
 731   }
 732
 733   return false;
 734 }
 735
 736 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 737 {
 738   switch (addr)
 739   {
 740     case 0:
 741       if (len <= 4) {
 742         state.mip = set_field(state.mip, MIP_MSIP, bytes[0]);
 743         return true;
 744       }
 745       break;
 746   }
 747
 748   return false;
 749 }
 750
 751 void processor_t::trigger_updated()
 752 {
 753   mmu->flush_tlb();
 754   mmu->check_triggers_fetch = false;
 755   mmu->check_triggers_load = false;
 756   mmu->check_triggers_store = false;
 757
 758   for (unsigned i = 0; i < state.num_triggers; i++) {
 759     if (state.mcontrol[i].execute) {
 760       mmu->check_triggers_fetch = true;
 761     }
 762     if (state.mcontrol[i].load) {
 763       mmu->check_triggers_load = true;
 764     }
 765     if (state.mcontrol[i].store) {
 766       mmu->check_triggers_store = true;
 767     }
 768   }
 769 }