riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "htif.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
  23   : sim(sim), ext(NULL), disassembler(new disassembler_t),
  24     id(id), run(false), debug(false)
  25 {
  26   parse_isa_string(isa);
  27
  28   mmu = new mmu_t(sim->mem, sim->memsz);
  29   mmu->set_processor(this);
  30
  31   reset(true);
  32
  33   #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
  34   #include "encoding.h"
  35   #undef DECLARE_INSN
  36   build_opcode_map();
  37 }
  38
  39 processor_t::~processor_t()
  40 {
  41 #ifdef RISCV_ENABLE_HISTOGRAM
  42   if (histogram_enabled)
  43   {
  44     fprintf(stderr, "PC Histogram size:%lu\n", pc_histogram.size());
  45     for(auto iterator = pc_histogram.begin(); iterator != pc_histogram.end(); ++iterator) {
  46       fprintf(stderr, "%0lx %lu\n", (iterator->first << 2), iterator->second);
  47     }
  48   }
  49 #endif
  50
  51   delete mmu;
  52   delete disassembler;
  53 }
  54
  55 static void bad_isa_string(const char* isa)
  56 {
  57   fprintf(stderr, "error: bad --isa option %s\n", isa);
  58   abort();
  59 }
  60
  61 void processor_t::parse_isa_string(const char* isa)
  62 {
  63   const char* p = isa;
  64   const char* all_subsets = "IMAFDC";
  65
  66   max_xlen = 64;
  67   if (strncmp(p, "RV32", 4) == 0)
  68     max_xlen = 32, p += 4;
  69   else if (strncmp(p, "RV64", 4) == 0)
  70     p += 4;
  71   else if (strncmp(p, "RV", 2) == 0)
  72     p += 2;
  73
  74   if (!*p)
  75     p = all_subsets;
  76   else if (*p != 'I')
  77     bad_isa_string(isa);
  78
  79   memset(subsets, 0, sizeof(subsets));
  80
  81   while (*p) {
  82     if (auto next = strchr(all_subsets, *p)) {
  83       subsets[(int)*p] = true;
  84       all_subsets = next + 1;
  85       p++;
  86     } else if (*p == 'X') {
  87       const char* ext = p+1, *end = ext;
  88       while (islower(*end))
  89         end++;
  90       register_extension(find_extension(std::string(ext, end - ext).c_str())());
  91       p = end;
  92     } else {
  93       bad_isa_string(isa);
  94     }
  95   }
  96
  97   if (supports_extension('D') && !supports_extension('F'))
  98     bad_isa_string(isa);
  99 }
 100
 101 void state_t::reset()
 102 {
 103   memset(this, 0, sizeof(*this));
 104   mstatus = set_field(mstatus, MSTATUS_PRV, PRV_M);
 105   mstatus = set_field(mstatus, MSTATUS_PRV1, PRV_S);
 106   mstatus = set_field(mstatus, MSTATUS_PRV2, PRV_S);
 107   pc = 0x100;
 108   load_reservation = -1;
 109 }
 110
 111 void processor_t::set_debug(bool value)
 112 {
 113   debug = value;
 114   if (ext)
 115     ext->set_debug(value);
 116 }
 117
 118 void processor_t::set_histogram(bool value)
 119 {
 120   histogram_enabled = value;
 121 }
 122
 123 void processor_t::reset(bool value)
 124 {
 125   if (run == !value)
 126     return;
 127   run = !value;
 128
 129   state.reset();
 130   set_csr(CSR_MSTATUS, state.mstatus);
 131
 132   if (ext)
 133     ext->reset(); // reset the extension
 134 }
 135
 136 void processor_t::raise_interrupt(reg_t which)
 137 {
 138   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 139 }
 140
 141 void processor_t::take_interrupt()
 142 {
 143   int priv = get_field(state.mstatus, MSTATUS_PRV);
 144   int ie = get_field(state.mstatus, MSTATUS_IE);
 145
 146   if (priv < PRV_M || (priv == PRV_M && ie)) {
 147     if (get_field(state.mstatus, MSTATUS_MSIP))
 148       raise_interrupt(IRQ_IPI);
 149
 150     if (state.fromhost != 0)
 151       raise_interrupt(IRQ_HOST);
 152   }
 153
 154   if (priv < PRV_S || (priv == PRV_S && ie)) {
 155     if (get_field(state.mstatus, MSTATUS_SSIP))
 156       raise_interrupt(IRQ_IPI);
 157
 158     if (state.stip && get_field(state.mstatus, MSTATUS_STIE))
 159       raise_interrupt(IRQ_TIMER);
 160   }
 161 }
 162
 163 static void commit_log(state_t* state, reg_t pc, insn_t insn)
 164 {
 165 #ifdef RISCV_ENABLE_COMMITLOG
 166   if (get_field(state->mstatus, MSTATUS_IE)) {
 167     uint64_t mask = (insn.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn.length() * 8))) - 1;
 168     if (state->log_reg_write.addr) {
 169       fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ") %c%2" PRIu64 " 0x%016" PRIx64 "\n",
 170               pc,
 171               insn.bits() & mask,
 172               state->log_reg_write.addr & 1 ? 'f' : 'x',
 173               state->log_reg_write.addr >> 1,
 174               state->log_reg_write.data);
 175     } else {
 176       fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ")\n", pc, insn.bits() & mask);
 177     }
 178   }
 179   state->log_reg_write.addr = 0;
 180 #endif
 181 }
 182
 183 inline void processor_t::update_histogram(size_t pc)
 184 {
 185 #ifdef RISCV_ENABLE_HISTOGRAM
 186   size_t idx = pc >> 2;
 187   pc_histogram[idx]++;
 188 #endif
 189 }
 190
 191 static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
 192 {
 193   reg_t npc = fetch.func(p, fetch.insn, pc);
 194   commit_log(p->get_state(), pc, fetch.insn);
 195   p->update_histogram(pc);
 196   return npc;
 197 }
 198
 199 static void update_timer(state_t* state, size_t instret)
 200 {
 201   uint64_t count0 = (uint64_t)(uint32_t)state->scount;
 202   state->scount += instret;
 203   uint64_t before = count0 - state->stimecmp;
 204   if (int64_t(before ^ (before + instret)) < 0)
 205     state->stip = true;
 206 }
 207
 208 static size_t next_timer(state_t* state)
 209 {
 210   return state->stimecmp - (uint32_t)state->scount;
 211 }
 212
 213 void processor_t::step(size_t n)
 214 {
 215   size_t instret = 0;
 216   reg_t pc = state.pc;
 217   mmu_t* _mmu = mmu;
 218
 219   if (unlikely(!run || !n))
 220     return;
 221   n = std::min(n, next_timer(&state) | 1U);
 222
 223   #define maybe_serialize() \
 224    if (unlikely(pc == PC_SERIALIZE)) { \
 225      pc = state.pc; \
 226      state.serialized = true; \
 227      continue; \
 228    }
 229
 230   try
 231   {
 232     take_interrupt();
 233
 234     if (unlikely(debug))
 235     {
 236       while (instret < n)
 237       {
 238         insn_fetch_t fetch = mmu->load_insn(pc);
 239         if (!state.serialized)
 240           disasm(fetch.insn);
 241         pc = execute_insn(this, pc, fetch);
 242         maybe_serialize();
 243         instret++;
 244         state.pc = pc;
 245       }
 246     }
 247     else while (instret < n)
 248     {
 249       size_t idx = _mmu->icache_index(pc);
 250       auto ic_entry = _mmu->access_icache(pc);
 251
 252       #define ICACHE_ACCESS(idx) { \
 253         insn_fetch_t fetch = ic_entry->data; \
 254         ic_entry++; \
 255         pc = execute_insn(this, pc, fetch); \
 256         if (idx == mmu_t::ICACHE_ENTRIES-1) break; \
 257         if (unlikely(ic_entry->tag != pc)) break; \
 258         instret++; \
 259         state.pc = pc; \
 260       }
 261
 262       switch (idx) {
 263         #include "icache.h"
 264       }
 265
 266       maybe_serialize();
 267       instret++;
 268       state.pc = pc;
 269     }
 270   }
 271   catch(trap_t& t)
 272   {
 273     state.pc = take_trap(t, pc);
 274   }
 275
 276   update_timer(&state, instret);
 277 }
 278
 279 void processor_t::push_privilege_stack()
 280 {
 281   reg_t s = state.mstatus;
 282   s = set_field(s, MSTATUS_PRV2, get_field(state.mstatus, MSTATUS_PRV1));
 283   s = set_field(s, MSTATUS_IE2, get_field(state.mstatus, MSTATUS_IE1));
 284   s = set_field(s, MSTATUS_PRV1, get_field(state.mstatus, MSTATUS_PRV));
 285   s = set_field(s, MSTATUS_IE1, get_field(state.mstatus, MSTATUS_IE));
 286   s = set_field(s, MSTATUS_PRV, PRV_M);
 287   s = set_field(s, MSTATUS_MPRV, PRV_M);
 288   s = set_field(s, MSTATUS_IE, 0);
 289   set_csr(CSR_MSTATUS, s);
 290 }
 291
 292 void processor_t::pop_privilege_stack()
 293 {
 294   reg_t s = state.mstatus;
 295   s = set_field(s, MSTATUS_PRV, get_field(state.mstatus, MSTATUS_PRV1));
 296   s = set_field(s, MSTATUS_IE, get_field(state.mstatus, MSTATUS_IE1));
 297   s = set_field(s, MSTATUS_PRV1, get_field(state.mstatus, MSTATUS_PRV2));
 298   s = set_field(s, MSTATUS_IE1, get_field(state.mstatus, MSTATUS_IE2));
 299   s = set_field(s, MSTATUS_PRV2, PRV_U);
 300   s = set_field(s, MSTATUS_IE2, 1);
 301   set_csr(CSR_MSTATUS, s);
 302 }
 303
 304 reg_t processor_t::take_trap(trap_t& t, reg_t epc)
 305 {
 306   if (debug)
 307     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 308             id, t.name(), epc);
 309
 310   reg_t tvec = 0x40 * get_field(state.mstatus, MSTATUS_PRV);
 311   push_privilege_stack();
 312   yield_load_reservation();
 313   state.mcause = t.cause();
 314   state.mepc = epc;
 315   t.side_effects(&state); // might set badvaddr etc.
 316   return tvec;
 317 }
 318
 319 void processor_t::deliver_ipi()
 320 {
 321   state.mstatus |= MSTATUS_MSIP;
 322 }
 323
 324 void processor_t::disasm(insn_t insn)
 325 {
 326   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 327   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 328           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 329 }
 330
 331 static bool validate_priv(reg_t priv)
 332 {
 333   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 334 }
 335
 336 static bool validate_arch(int max_xlen, reg_t arch)
 337 {
 338   if (max_xlen == 64 && arch == UA_RV64)
 339     return true;
 340   return arch == UA_RV32;
 341 }
 342
 343 static bool validate_vm(int max_xlen, reg_t vm)
 344 {
 345   if (max_xlen == 64 && vm == VM_SV39)
 346     return true;
 347   if (max_xlen == 32 && vm == VM_SV32)
 348     return true;
 349   return vm == VM_MBARE;
 350 }
 351
 352 void processor_t::set_csr(int which, reg_t val)
 353 {
 354   switch (which)
 355   {
 356     case CSR_FFLAGS:
 357       dirty_fp_state;
 358       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 359       break;
 360     case CSR_FRM:
 361       dirty_fp_state;
 362       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 363       break;
 364     case CSR_FCSR:
 365       dirty_fp_state;
 366       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 367       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 368       break;
 369     case CSR_SCYCLE:
 370     case CSR_STIME:
 371     case CSR_SINSTRET:
 372       state.scount = val; break;
 373     case CSR_SCYCLEH:
 374     case CSR_STIMEH:
 375     case CSR_SINSTRETH:
 376       state.scount = (val << 32) | (uint32_t)state.scount;
 377       break;
 378     case CSR_MSTATUS:
 379     {
 380       if ((val ^ state.mstatus) & (MSTATUS_VM | MSTATUS_PRV | MSTATUS_MPRV))
 381         mmu->flush_tlb();
 382
 383       reg_t mask = MSTATUS_SSIP | MSTATUS_MSIP | MSTATUS_IE | MSTATUS_IE1
 384                    | MSTATUS_IE2 | MSTATUS_IE3 | MSTATUS_STIE | MSTATUS_FS;
 385       if (ext)
 386         mask |= MSTATUS_XS;
 387       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 388
 389       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 390         state.mstatus = (state.mstatus & ~MSTATUS_VM) | (val & MSTATUS_VM);
 391       if (validate_priv(get_field(val, MSTATUS_MPRV)))
 392         state.mstatus = (state.mstatus & ~MSTATUS_MPRV) | (val & MSTATUS_MPRV);
 393       if (validate_priv(get_field(val, MSTATUS_PRV)))
 394         state.mstatus = (state.mstatus & ~MSTATUS_PRV) | (val & MSTATUS_PRV);
 395       if (validate_priv(get_field(val, MSTATUS_PRV1)))
 396         state.mstatus = (state.mstatus & ~MSTATUS_PRV1) | (val & MSTATUS_PRV1);
 397       if (validate_priv(get_field(val, MSTATUS_PRV2)))
 398         state.mstatus = (state.mstatus & ~MSTATUS_PRV2) | (val & MSTATUS_PRV2);
 399       if (validate_priv(get_field(val, MSTATUS_PRV3)))
 400         state.mstatus = (state.mstatus & ~MSTATUS_PRV3) | (val & MSTATUS_PRV3);
 401
 402       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 403       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 404       xlen = 32;
 405       if (max_xlen == 32) {
 406         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 407       } else {
 408         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 409
 410         if (validate_arch(max_xlen, get_field(val, MSTATUS64_UA)))
 411           state.mstatus = (state.mstatus & ~MSTATUS64_UA) | (val & MSTATUS64_UA);
 412         if (validate_arch(max_xlen, get_field(val, MSTATUS64_SA)))
 413           state.mstatus = (state.mstatus & ~MSTATUS64_SA) | (val & MSTATUS64_SA);
 414         switch (get_field(state.mstatus, MSTATUS_PRV)) {
 415           case PRV_U: if (get_field(state.mstatus, MSTATUS64_UA)) xlen = 64; break;
 416           case PRV_S: if (get_field(state.mstatus, MSTATUS64_SA)) xlen = 64; break;
 417           case PRV_M: xlen = 64; break;
 418           default: abort();
 419         }
 420       }
 421       break;
 422     }
 423     case CSR_SSTATUS:
 424     {
 425       reg_t ms = state.mstatus;
 426       ms = set_field(ms, MSTATUS_SSIP, get_field(val, SSTATUS_SIP));
 427       ms = set_field(ms, MSTATUS_IE, get_field(val, SSTATUS_IE));
 428       ms = set_field(ms, MSTATUS_IE1, get_field(val, SSTATUS_PIE));
 429       ms = set_field(ms, MSTATUS_PRV1, get_field(val, SSTATUS_PS));
 430       ms = set_field(ms, MSTATUS64_UA, get_field(val, SSTATUS_UA));
 431       ms = set_field(ms, MSTATUS_STIE, get_field(val, SSTATUS_TIE));
 432       ms = set_field(ms, MSTATUS_FS, get_field(val, SSTATUS_FS));
 433       ms = set_field(ms, MSTATUS_XS, get_field(val, SSTATUS_XS));
 434       return set_csr(CSR_MSTATUS, ms);
 435     }
 436     case CSR_SEPC: state.sepc = val; break;
 437     case CSR_STVEC: state.stvec = val & ~3; break;
 438     case CSR_STIMECMP:
 439       state.stip = false;
 440       state.stimecmp = val;
 441       break;
 442     case CSR_SPTBR: state.sptbr = val & ~(PGSIZE-1); break;
 443     case CSR_SSCRATCH: state.sscratch = val; break;
 444     case CSR_MEPC: state.mepc = val; break;
 445     case CSR_MSCRATCH: state.mscratch = val; break;
 446     case CSR_MCAUSE: state.mcause = val; break;
 447     case CSR_MBADADDR: state.mbadaddr = val; break;
 448     case CSR_SEND_IPI: sim->send_ipi(val); break;
 449     case CSR_TOHOST:
 450       if (state.tohost == 0)
 451         state.tohost = val;
 452       break;
 453     case CSR_FROMHOST: state.fromhost = val; break;
 454   }
 455 }
 456
 457 reg_t processor_t::get_csr(int which)
 458 {
 459   switch (which)
 460   {
 461     case CSR_FFLAGS:
 462       require_fp;
 463       return state.fflags;
 464     case CSR_FRM:
 465       require_fp;
 466       return state.frm;
 467     case CSR_FCSR:
 468       require_fp;
 469       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 470     case CSR_CYCLE:
 471     case CSR_TIME:
 472     case CSR_INSTRET:
 473     case CSR_SCYCLE:
 474     case CSR_STIME:
 475     case CSR_SINSTRET:
 476       return state.scount;
 477     case CSR_CYCLEH:
 478     case CSR_TIMEH:
 479     case CSR_INSTRETH:
 480     case CSR_SCYCLEH:
 481     case CSR_STIMEH:
 482     case CSR_SINSTRETH:
 483       if (xlen == 64)
 484         break;
 485       return state.scount >> 32;
 486     case CSR_SSTATUS:
 487     {
 488       reg_t ss = 0;
 489       ss = set_field(ss, SSTATUS_SIP, get_field(state.mstatus, MSTATUS_SSIP));
 490       ss = set_field(ss, SSTATUS_IE, get_field(state.mstatus, MSTATUS_IE));
 491       ss = set_field(ss, SSTATUS_PIE, get_field(state.mstatus, MSTATUS_IE1));
 492       ss = set_field(ss, SSTATUS_PS, get_field(state.mstatus, MSTATUS_PRV1));
 493       ss = set_field(ss, SSTATUS_UA, get_field(state.mstatus, MSTATUS64_UA));
 494       ss = set_field(ss, SSTATUS_TIE, get_field(state.mstatus, MSTATUS_STIE));
 495       ss = set_field(ss, SSTATUS_TIP, state.stip);
 496       ss = set_field(ss, SSTATUS_FS, get_field(state.mstatus, MSTATUS_FS));
 497       ss = set_field(ss, SSTATUS_XS, get_field(state.mstatus, MSTATUS_XS));
 498       if (get_field(state.mstatus, MSTATUS64_SD))
 499         ss = set_field(ss, (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD), 1);
 500       return ss;
 501     }
 502     case CSR_SEPC: return state.sepc;
 503     case CSR_SBADADDR: return state.sbadaddr;
 504     case CSR_STVEC: return state.stvec;
 505     case CSR_STIMECMP: return state.stimecmp;
 506     case CSR_SCAUSE:
 507       if (max_xlen > xlen)
 508         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 509       return state.scause;
 510     case CSR_SPTBR: return state.sptbr;
 511     case CSR_SASID: return 0;
 512     case CSR_SSCRATCH: return state.sscratch;
 513     case CSR_MSTATUS: return state.mstatus;
 514     case CSR_MEPC: return state.mepc;
 515     case CSR_MSCRATCH: return state.mscratch;
 516     case CSR_MCAUSE: return state.mcause;
 517     case CSR_MBADADDR: return state.mbadaddr;
 518     case CSR_TOHOST:
 519       sim->get_htif()->tick(); // not necessary, but faster
 520       return state.tohost;
 521     case CSR_FROMHOST:
 522       sim->get_htif()->tick(); // not necessary, but faster
 523       return state.fromhost;
 524     case CSR_SEND_IPI: return 0;
 525     case CSR_HARTID: return id;
 526     case CSR_UARCH0:
 527     case CSR_UARCH1:
 528     case CSR_UARCH2:
 529     case CSR_UARCH3:
 530     case CSR_UARCH4:
 531     case CSR_UARCH5:
 532     case CSR_UARCH6:
 533     case CSR_UARCH7:
 534     case CSR_UARCH8:
 535     case CSR_UARCH9:
 536     case CSR_UARCH10:
 537     case CSR_UARCH11:
 538     case CSR_UARCH12:
 539     case CSR_UARCH13:
 540     case CSR_UARCH14:
 541     case CSR_UARCH15:
 542       return 0;
 543   }
 544   throw trap_illegal_instruction();
 545 }
 546
 547 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 548 {
 549   throw trap_illegal_instruction();
 550 }
 551
 552 insn_func_t processor_t::decode_insn(insn_t insn)
 553 {
 554   size_t mask = opcode_map.size()-1;
 555   insn_desc_t* desc = opcode_map[insn.bits() & mask];
 556
 557   while ((insn.bits() & desc->mask) != desc->match)
 558     desc++;
 559
 560   return xlen == 64 ? desc->rv64 : desc->rv32;
 561 }
 562
 563 void processor_t::register_insn(insn_desc_t desc)
 564 {
 565   assert(desc.mask & 1);
 566   instructions.push_back(desc);
 567 }
 568
 569 void processor_t::build_opcode_map()
 570 {
 571   size_t buckets = -1;
 572   for (auto& inst : instructions)
 573     while ((inst.mask & buckets) != buckets)
 574       buckets /= 2;
 575   buckets++;
 576
 577   struct cmp {
 578     decltype(insn_desc_t::match) mask;
 579     cmp(decltype(mask) mask) : mask(mask) {}
 580     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 581       if ((lhs.match & mask) != (rhs.match & mask))
 582         return (lhs.match & mask) < (rhs.match & mask);
 583       return lhs.match < rhs.match;
 584     }
 585   };
 586   std::sort(instructions.begin(), instructions.end(), cmp(buckets-1));
 587
 588   opcode_map.resize(buckets);
 589   opcode_store.resize(instructions.size() + 1);
 590
 591   size_t j = 0;
 592   for (size_t b = 0, i = 0; b < buckets; b++)
 593   {
 594     opcode_map[b] = &opcode_store[j];
 595     while (i < instructions.size() && b == (instructions[i].match & (buckets-1)))
 596       opcode_store[j++] = instructions[i++];
 597   }
 598
 599   assert(j == opcode_store.size()-1);
 600   opcode_store[j].match = opcode_store[j].mask = 0;
 601   opcode_store[j].rv32 = &illegal_instruction;
 602   opcode_store[j].rv64 = &illegal_instruction;
 603 }
 604
 605 void processor_t::register_extension(extension_t* x)
 606 {
 607   for (auto insn : x->get_instructions())
 608     register_insn(insn);
 609   build_opcode_map();
 610   for (auto disasm_insn : x->get_disasms())
 611     disassembler->add_insn(disasm_insn);
 612   if (ext != NULL)
 613     throw std::logic_error("only one extension may be registered");
 614   ext = x;
 615   x->set_processor(this);
 616 }