riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "htif.h"
   9 #include "disasm.h"
  10 #include "icache.h"
  11 #include <cinttypes>
  12 #include <cmath>
  13 #include <cstdlib>
  14 #include <iostream>
  15 #include <assert.h>
  16 #include <limits.h>
  17 #include <stdexcept>
  18 #include <algorithm>
  19
  20 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
  21   : sim(_sim), mmu(_mmu), ext(NULL), disassembler(new disassembler_t),
  22     id(_id), run(false), debug(false)
  23 {
  24   reset(true);
  25   mmu->set_processor(this);
  26
  27   #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
  28   #include "encoding.h"
  29   #undef DECLARE_INSN
  30   build_opcode_map();
  31 }
  32
  33 processor_t::~processor_t()
  34 {
  35   delete disassembler;
  36 }
  37
  38 void state_t::reset()
  39 {
  40   // the ISA guarantees on boot that the PC is 0x2000 and the the processor
  41   // is in supervisor mode, and in 64-bit mode, if supported, with traps
  42   // and virtual memory disabled.
  43   sr = SR_S | SR_S64 | SR_U64;
  44   pc = 0x2000;
  45
  46   // the following state is undefined upon boot-up,
  47   // but we zero it for determinism
  48   XPR.reset();
  49   FPR.reset();
  50
  51   epc = 0;
  52   badvaddr = 0;
  53   evec = 0;
  54   ptbr = 0;
  55   pcr_k0 = 0;
  56   pcr_k1 = 0;
  57   cause = 0;
  58   tohost = 0;
  59   fromhost = 0;
  60   count = 0;
  61   compare = 0;
  62   fflags = 0;
  63   frm = 0;
  64
  65   load_reservation = -1;
  66 }
  67
  68 void processor_t::set_debug(bool value)
  69 {
  70   debug = value;
  71   if (ext)
  72     ext->set_debug(value);
  73 }
  74
  75 void processor_t::reset(bool value)
  76 {
  77   if (run == !value)
  78     return;
  79   run = !value;
  80
  81   state.reset(); // reset the core
  82   set_pcr(CSR_STATUS, state.sr);
  83
  84   if (ext)
  85     ext->reset(); // reset the extension
  86 }
  87
  88 void processor_t::take_interrupt()
  89 {
  90   uint32_t interrupts = (state.sr & SR_IP) >> SR_IP_SHIFT;
  91   interrupts &= (state.sr & SR_IM) >> SR_IM_SHIFT;
  92
  93   if (interrupts && (state.sr & SR_EI))
  94     for (int i = 0; ; i++, interrupts >>= 1)
  95       if (interrupts & 1)
  96         throw trap_t((1ULL << ((state.sr & SR_S64) ? 63 : 31)) + i);
  97 }
  98
  99 static void commit_log(state_t* state, insn_t insn)
 100 {
 101 #ifdef RISCV_ENABLE_COMMITLOG
 102   if (state->sr & SR_EI) {
 103     if (state->log_reg_write.addr) {
 104       fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx32 ") %c%2u 0x%016" PRIx64 "\n",
 105               state->pc, insn.bits(),
 106               state->log_reg_write.addr & 1 ? 'f' : 'x',
 107               state->log_reg_write.addr >> 1, state->log_reg_write.data);
 108     }
 109     else {
 110       fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx32 ")\n",
 111               state->pc, insn.bits());
 112     }
 113   }
 114   state->log_reg_write.addr = 0;
 115 #endif
 116 }
 117
 118 void processor_t::step(size_t n)
 119 {
 120   if(!run)
 121     return;
 122
 123   mmu_t* _mmu = mmu;
 124   auto count32 = decltype(state.compare)(state.count);
 125   bool count_le_compare = count32 <= state.compare;
 126   n = std::min(n, size_t(state.compare - count32) | 1);
 127
 128   try
 129   {
 130     take_interrupt();
 131
 132     if (debug) // print out instructions as we go
 133     {
 134       for (size_t i = 0; i < n; state.count++, i++)
 135       {
 136         insn_fetch_t fetch = mmu->load_insn(state.pc);
 137         disasm(fetch.insn.insn);
 138         reg_t npc = fetch.func(this, fetch.insn.insn, state.pc);
 139         commit_log(&state, fetch.insn.insn);
 140         state.pc = npc;
 141       }
 142     }
 143     else while (n > 0)
 144     {
 145       size_t idx = (state.pc / sizeof(insn_t)) % ICACHE_SIZE;
 146       auto ic_entry = _mmu->access_icache(state.pc), ic_entry_init = ic_entry;
 147
 148       #define ICACHE_ACCESS(idx) { \
 149         insn_t insn = ic_entry->data.insn.insn; \
 150         insn_func_t func = ic_entry->data.func; \
 151         ic_entry++; \
 152         reg_t npc = func(this, insn, state.pc); \
 153         commit_log(&state, insn); \
 154         state.pc = npc; \
 155         if (idx < ICACHE_SIZE-1 && unlikely(ic_entry->tag != state.pc)) break; \
 156       }
 157
 158       switch (idx)
 159       {
 160         ICACHE_SWITCH; // auto-generated into icache.h
 161       }
 162
 163       size_t i = ic_entry - ic_entry_init;
 164       state.count += i;
 165       if (i >= n)
 166         break;
 167       n -= i;
 168     }
 169   }
 170   catch(trap_t& t)
 171   {
 172     take_trap(t);
 173   }
 174
 175   bool count_ge_compare =
 176     uint64_t(n) + decltype(state.compare)(state.count) >= state.compare;
 177   if (count_le_compare && count_ge_compare)
 178     set_interrupt(IRQ_TIMER, true);
 179 }
 180
 181 void processor_t::take_trap(trap_t& t)
 182 {
 183   if (debug)
 184     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 185             id, t.name(), state.pc);
 186
 187   // switch to supervisor, set previous supervisor bit, disable interrupts
 188   set_pcr(CSR_STATUS, (((state.sr & ~SR_EI) | SR_S) & ~SR_PS & ~SR_PEI) |
 189                       ((state.sr & SR_S) ? SR_PS : 0) |
 190                       ((state.sr & SR_EI) ? SR_PEI : 0));
 191
 192   yield_load_reservation();
 193   state.cause = t.cause();
 194   state.epc = state.pc;
 195   state.pc = state.evec;
 196
 197   t.side_effects(&state); // might set badvaddr etc.
 198 }
 199
 200 void processor_t::deliver_ipi()
 201 {
 202   if (run)
 203     set_pcr(CSR_CLEAR_IPI, 1);
 204 }
 205
 206 void processor_t::disasm(insn_t insn)
 207 {
 208   // the disassembler is stateless, so we share it
 209   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx32 ") %s\n",
 210           id, state.pc, insn.bits(), disassembler->disassemble(insn).c_str());
 211 }
 212
 213 reg_t processor_t::set_pcr(int which, reg_t val)
 214 {
 215   reg_t old_pcr = get_pcr(which);
 216
 217   switch (which)
 218   {
 219     case CSR_FFLAGS:
 220       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 221       break;
 222     case CSR_FRM:
 223       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 224       break;
 225     case CSR_FCSR:
 226       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 227       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 228       break;
 229     case CSR_STATUS:
 230       state.sr = (val & ~SR_IP) | (state.sr & SR_IP);
 231 #ifndef RISCV_ENABLE_64BIT
 232       state.sr &= ~(SR_S64 | SR_U64);
 233 #endif
 234 #ifndef RISCV_ENABLE_FPU
 235       state.sr &= ~SR_EF;
 236 #endif
 237       if (!ext)
 238         state.sr &= ~SR_EA;
 239       state.sr &= ~SR_ZERO;
 240       rv64 = (state.sr & SR_S) ? (state.sr & SR_S64) : (state.sr & SR_U64);
 241       mmu->flush_tlb();
 242       break;
 243     case CSR_EPC:
 244       state.epc = val;
 245       break;
 246     case CSR_EVEC:
 247       state.evec = val & ~3;
 248       break;
 249     case CSR_COUNT:
 250       state.count = val;
 251       break;
 252     case CSR_COUNTH:
 253       state.count = (val << 32) | (uint32_t)state.count;
 254       break;
 255     case CSR_COMPARE:
 256       set_interrupt(IRQ_TIMER, false);
 257       state.compare = val;
 258       break;
 259     case CSR_PTBR:
 260       state.ptbr = val & ~(PGSIZE-1);
 261       break;
 262     case CSR_SEND_IPI:
 263       sim->send_ipi(val);
 264       break;
 265     case CSR_CLEAR_IPI:
 266       set_interrupt(IRQ_IPI, val & 1);
 267       break;
 268     case CSR_SUP0:
 269       state.pcr_k0 = val;
 270       break;
 271     case CSR_SUP1:
 272       state.pcr_k1 = val;
 273       break;
 274     case CSR_TOHOST:
 275       if (state.tohost == 0)
 276         state.tohost = val;
 277       break;
 278     case CSR_FROMHOST:
 279       set_fromhost(val);
 280       break;
 281   }
 282
 283   return old_pcr;
 284 }
 285
 286 void processor_t::set_fromhost(reg_t val)
 287 {
 288   set_interrupt(IRQ_HOST, val != 0);
 289   state.fromhost = val;
 290 }
 291
 292 reg_t processor_t::get_pcr(int which)
 293 {
 294   switch (which)
 295   {
 296     case CSR_FFLAGS:
 297       return state.fflags;
 298     case CSR_FRM:
 299       return state.frm;
 300     case CSR_FCSR:
 301       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 302     case CSR_STATUS:
 303       return state.sr;
 304     case CSR_EPC:
 305       return state.epc;
 306     case CSR_BADVADDR:
 307       return state.badvaddr;
 308     case CSR_EVEC:
 309       return state.evec;
 310     case CSR_CYCLE:
 311     case CSR_TIME:
 312     case CSR_INSTRET:
 313     case CSR_COUNT:
 314       return state.count;
 315     case CSR_CYCLEH:
 316     case CSR_TIMEH:
 317     case CSR_INSTRETH:
 318     case CSR_COUNTH:
 319       if (rv64)
 320         break;
 321       return state.count >> 32;
 322     case CSR_COMPARE:
 323       return state.compare;
 324     case CSR_CAUSE:
 325       return state.cause;
 326     case CSR_PTBR:
 327       return state.ptbr;
 328     case CSR_SEND_IPI:
 329     case CSR_CLEAR_IPI:
 330       return 0;
 331     case CSR_ASID:
 332       return 0;
 333     case CSR_FATC:
 334       mmu->flush_tlb();
 335       return 0;
 336     case CSR_HARTID:
 337       return id;
 338     case CSR_IMPL:
 339       return 1;
 340     case CSR_SUP0:
 341       return state.pcr_k0;
 342     case CSR_SUP1:
 343       return state.pcr_k1;
 344     case CSR_TOHOST:
 345       sim->get_htif()->tick(); // not necessary, but faster
 346       return state.tohost;
 347     case CSR_FROMHOST:
 348       sim->get_htif()->tick(); // not necessary, but faster
 349       return state.fromhost;
 350   }
 351   throw trap_illegal_instruction();
 352 }
 353
 354 void processor_t::set_interrupt(int which, bool on)
 355 {
 356   uint32_t mask = (1 << (which + SR_IP_SHIFT)) & SR_IP;
 357   if (on)
 358     state.sr |= mask;
 359   else
 360     state.sr &= ~mask;
 361 }
 362
 363 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 364 {
 365   throw trap_illegal_instruction();
 366 }
 367
 368 insn_func_t processor_t::decode_insn(insn_t insn)
 369 {
 370   size_t mask = opcode_map.size()-1;
 371   insn_desc_t* desc = opcode_map[insn.bits() & mask];
 372
 373   while ((insn.bits() & desc->mask) != desc->match)
 374     desc++;
 375
 376   return rv64 ? desc->rv64 : desc->rv32;
 377 }
 378
 379 void processor_t::register_insn(insn_desc_t desc)
 380 {
 381   assert(desc.mask & 1);
 382   instructions.push_back(desc);
 383 }
 384
 385 void processor_t::build_opcode_map()
 386 {
 387   size_t buckets = -1;
 388   for (auto& inst : instructions)
 389     while ((inst.mask & buckets) != buckets)
 390       buckets /= 2;
 391   buckets++;
 392
 393   struct cmp {
 394     decltype(insn_desc_t::match) mask;
 395     cmp(decltype(mask) mask) : mask(mask) {}
 396     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 397       if ((lhs.match & mask) != (rhs.match & mask))
 398         return (lhs.match & mask) < (rhs.match & mask);
 399       return lhs.match < rhs.match;
 400     }
 401   };
 402   std::sort(instructions.begin(), instructions.end(), cmp(buckets-1));
 403
 404   opcode_map.resize(buckets);
 405   opcode_store.resize(instructions.size() + 1);
 406
 407   size_t j = 0;
 408   for (size_t b = 0, i = 0; b < buckets; b++)
 409   {
 410     opcode_map[b] = &opcode_store[j];
 411     while (i < instructions.size() && b == (instructions[i].match & (buckets-1)))
 412       opcode_store[j++] = instructions[i++];
 413   }
 414
 415   assert(j == opcode_store.size()-1);
 416   opcode_store[j].match = opcode_store[j].mask = 0;
 417   opcode_store[j].rv32 = &illegal_instruction;
 418   opcode_store[j].rv64 = &illegal_instruction;
 419 }
 420
 421 void processor_t::register_extension(extension_t* x)
 422 {
 423   for (auto insn : x->get_instructions())
 424     register_insn(insn);
 425   build_opcode_map();
 426   for (auto disasm_insn : x->get_disasms())
 427     disassembler->add_insn(disasm_insn);
 428   if (ext != NULL)
 429     throw std::logic_error("only one extension may be registered");
 430   ext = x;
 431   x->set_processor(this);
 432 }