1 // See LICENSE for license details.
20 processor_t::processor_t(sim_t
* _sim
, mmu_t
* _mmu
, uint32_t _id
)
21 : sim(_sim
), mmu(_mmu
), ext(NULL
), disassembler(new disassembler_t
),
22 id(_id
), run(false), debug(false)
25 mmu
->set_processor(this);
27 #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
33 processor_t::~processor_t()
40 // the ISA guarantees on boot that the PC is 0x2000 and the the processor
41 // is in supervisor mode, and in 64-bit mode, if supported, with traps
42 // and virtual memory disabled.
43 sr
= SR_S
| SR_S64
| SR_U64
;
46 // the following state is undefined upon boot-up,
47 // but we zero it for determinism
65 load_reservation
= -1;
68 void processor_t::set_debug(bool value
)
72 ext
->set_debug(value
);
75 void processor_t::reset(bool value
)
81 state
.reset(); // reset the core
82 set_pcr(CSR_STATUS
, state
.sr
);
85 ext
->reset(); // reset the extension
88 void processor_t::take_interrupt()
90 uint32_t interrupts
= (state
.sr
& SR_IP
) >> SR_IP_SHIFT
;
91 interrupts
&= (state
.sr
& SR_IM
) >> SR_IM_SHIFT
;
93 if (interrupts
&& (state
.sr
& SR_EI
))
94 for (int i
= 0; ; i
++, interrupts
>>= 1)
96 throw trap_t((1ULL << ((state
.sr
& SR_S64
) ? 63 : 31)) + i
);
99 static void commit_log(state_t
* state
, insn_t insn
)
101 #ifdef RISCV_ENABLE_COMMITLOG
102 if (state
->sr
& SR_EI
) {
103 if (state
->log_reg_write
.addr
) {
104 fprintf(stderr
, "0x%016" PRIx64
" (0x%08" PRIx32
") %c%2u 0x%016" PRIx64
"\n",
105 state
->pc
, insn
.bits(),
106 state
->log_reg_write
.addr
& 1 ? 'f' : 'x',
107 state
->log_reg_write
.addr
>> 1, state
->log_reg_write
.data
);
110 fprintf(stderr
, "0x%016" PRIx64
" (0x%08" PRIx32
")\n",
111 state
->pc
, insn
.bits());
114 state
->log_reg_write
.addr
= 0;
118 void processor_t::step(size_t n
)
124 auto count32
= decltype(state
.compare
)(state
.count
);
125 bool count_le_compare
= count32
<= state
.compare
;
126 n
= std::min(n
, size_t(state
.compare
- count32
) | 1);
132 if (debug
) // print out instructions as we go
134 for (size_t i
= 0; i
< n
; state
.count
++, i
++)
136 insn_fetch_t fetch
= mmu
->load_insn(state
.pc
);
137 disasm(fetch
.insn
.insn
);
138 reg_t npc
= fetch
.func(this, fetch
.insn
.insn
, state
.pc
);
139 commit_log(&state
, fetch
.insn
.insn
);
145 size_t idx
= (state
.pc
/ sizeof(insn_t
)) % ICACHE_SIZE
;
146 auto ic_entry
= _mmu
->access_icache(state
.pc
), ic_entry_init
= ic_entry
;
148 #define ICACHE_ACCESS(idx) { \
149 insn_t insn = ic_entry->data.insn.insn; \
150 insn_func_t func = ic_entry->data.func; \
152 reg_t npc = func(this, insn, state.pc); \
153 commit_log(&state, insn); \
155 if (idx < ICACHE_SIZE-1 && unlikely(ic_entry->tag != state.pc)) break; \
160 ICACHE_SWITCH
; // auto-generated into icache.h
163 size_t i
= ic_entry
- ic_entry_init
;
175 bool count_ge_compare
=
176 uint64_t(n
) + decltype(state
.compare
)(state
.count
) >= state
.compare
;
177 if (count_le_compare
&& count_ge_compare
)
178 set_interrupt(IRQ_TIMER
, true);
181 void processor_t::take_trap(trap_t
& t
)
184 fprintf(stderr
, "core %3d: exception %s, epc 0x%016" PRIx64
"\n",
185 id
, t
.name(), state
.pc
);
187 // switch to supervisor, set previous supervisor bit, disable interrupts
188 set_pcr(CSR_STATUS
, (((state
.sr
& ~SR_EI
) | SR_S
) & ~SR_PS
& ~SR_PEI
) |
189 ((state
.sr
& SR_S
) ? SR_PS
: 0) |
190 ((state
.sr
& SR_EI
) ? SR_PEI
: 0));
192 yield_load_reservation();
193 state
.cause
= t
.cause();
194 state
.epc
= state
.pc
;
195 state
.pc
= state
.evec
;
197 t
.side_effects(&state
); // might set badvaddr etc.
200 void processor_t::deliver_ipi()
203 set_pcr(CSR_CLEAR_IPI
, 1);
206 void processor_t::disasm(insn_t insn
)
208 // the disassembler is stateless, so we share it
209 fprintf(stderr
, "core %3d: 0x%016" PRIx64
" (0x%08" PRIx32
") %s\n",
210 id
, state
.pc
, insn
.bits(), disassembler
->disassemble(insn
).c_str());
213 reg_t
processor_t::set_pcr(int which
, reg_t val
)
215 reg_t old_pcr
= get_pcr(which
);
220 state
.fflags
= val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
);
223 state
.frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
226 state
.fflags
= (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
;
227 state
.frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
230 state
.sr
= (val
& ~SR_IP
) | (state
.sr
& SR_IP
);
231 #ifndef RISCV_ENABLE_64BIT
232 state
.sr
&= ~(SR_S64
| SR_U64
);
234 #ifndef RISCV_ENABLE_FPU
239 state
.sr
&= ~SR_ZERO
;
240 rv64
= (state
.sr
& SR_S
) ? (state
.sr
& SR_S64
) : (state
.sr
& SR_U64
);
247 state
.evec
= val
& ~3;
253 state
.count
= (val
<< 32) | (uint32_t)state
.count
;
256 set_interrupt(IRQ_TIMER
, false);
260 state
.ptbr
= val
& ~(PGSIZE
-1);
266 set_interrupt(IRQ_IPI
, val
& 1);
275 if (state
.tohost
== 0)
286 void processor_t::set_fromhost(reg_t val
)
288 set_interrupt(IRQ_HOST
, val
!= 0);
289 state
.fromhost
= val
;
292 reg_t
processor_t::get_pcr(int which
)
301 return (state
.fflags
<< FSR_AEXC_SHIFT
) | (state
.frm
<< FSR_RD_SHIFT
);
307 return state
.badvaddr
;
321 return state
.count
>> 32;
323 return state
.compare
;
345 sim
->get_htif()->tick(); // not necessary, but faster
348 sim
->get_htif()->tick(); // not necessary, but faster
349 return state
.fromhost
;
351 throw trap_illegal_instruction();
354 void processor_t::set_interrupt(int which
, bool on
)
356 uint32_t mask
= (1 << (which
+ SR_IP_SHIFT
)) & SR_IP
;
363 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
)
365 throw trap_illegal_instruction();
368 insn_func_t
processor_t::decode_insn(insn_t insn
)
370 size_t mask
= opcode_map
.size()-1;
371 insn_desc_t
* desc
= opcode_map
[insn
.bits() & mask
];
373 while ((insn
.bits() & desc
->mask
) != desc
->match
)
376 return rv64
? desc
->rv64
: desc
->rv32
;
379 void processor_t::register_insn(insn_desc_t desc
)
381 assert(desc
.mask
& 1);
382 instructions
.push_back(desc
);
385 void processor_t::build_opcode_map()
388 for (auto& inst
: instructions
)
389 while ((inst
.mask
& buckets
) != buckets
)
394 decltype(insn_desc_t::match
) mask
;
395 cmp(decltype(mask
) mask
) : mask(mask
) {}
396 bool operator()(const insn_desc_t
& lhs
, const insn_desc_t
& rhs
) {
397 if ((lhs
.match
& mask
) != (rhs
.match
& mask
))
398 return (lhs
.match
& mask
) < (rhs
.match
& mask
);
399 return lhs
.match
< rhs
.match
;
402 std::sort(instructions
.begin(), instructions
.end(), cmp(buckets
-1));
404 opcode_map
.resize(buckets
);
405 opcode_store
.resize(instructions
.size() + 1);
408 for (size_t b
= 0, i
= 0; b
< buckets
; b
++)
410 opcode_map
[b
] = &opcode_store
[j
];
411 while (i
< instructions
.size() && b
== (instructions
[i
].match
& (buckets
-1)))
412 opcode_store
[j
++] = instructions
[i
++];
415 assert(j
== opcode_store
.size()-1);
416 opcode_store
[j
].match
= opcode_store
[j
].mask
= 0;
417 opcode_store
[j
].rv32
= &illegal_instruction
;
418 opcode_store
[j
].rv64
= &illegal_instruction
;
421 void processor_t::register_extension(extension_t
* x
)
423 for (auto insn
: x
->get_instructions())
426 for (auto disasm_insn
: x
->get_disasms())
427 disassembler
->add_insn(disasm_insn
);
429 throw std::logic_error("only one extension may be registered");
431 x
->set_processor(this);