riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  23         bool halt_on_reset)
  24   : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
  25   halt_on_reset(halt_on_reset), last_pc(1), executions(1)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31   disassembler = new disassembler_t(max_xlen);
  32
  33   reset();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdqc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = "imafdc";
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87   isa |= 1L << ('u' - 'a'); // advertise support for user mode
  88
  89   while (*p) {
  90     isa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   if (supports_extension('Q') && !supports_extension('D'))
 110     bad_isa_string(str);
 111
 112   if (supports_extension('Q') && max_xlen < 64)
 113     bad_isa_string(str);
 114
 115   max_isa = isa;
 116 }
 117
 118 void state_t::reset()
 119 {
 120   memset(this, 0, sizeof(*this));
 121   prv = PRV_M;
 122   pc = DEFAULT_RSTVEC;
 123   load_reservation = -1;
 124   tselect = 0;
 125   for (unsigned int i = 0; i < num_triggers; i++)
 126     mcontrol[i].type = 2;
 127 }
 128
 129 void processor_t::set_debug(bool value)
 130 {
 131   debug = value;
 132   if (ext)
 133     ext->set_debug(value);
 134 }
 135
 136 void processor_t::set_histogram(bool value)
 137 {
 138   histogram_enabled = value;
 139 #ifndef RISCV_ENABLE_HISTOGRAM
 140   if (value) {
 141     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 142     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 143   }
 144 #endif
 145 }
 146
 147 void processor_t::reset()
 148 {
 149   state.reset();
 150   state.dcsr.halt = halt_on_reset;
 151   halt_on_reset = false;
 152   set_csr(CSR_MSTATUS, state.mstatus);
 153
 154   if (ext)
 155     ext->reset(); // reset the extension
 156 }
 157
 158 // Count number of contiguous 0 bits starting from the LSB.
 159 static int ctz(reg_t val)
 160 {
 161   int res = 0;
 162   if (val)
 163     while ((val & 1) == 0)
 164       val >>= 1, res++;
 165   return res;
 166 }
 167
 168 void processor_t::take_interrupt(reg_t pending_interrupts)
 169 {
 170   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 171   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 172   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 173
 174   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 175   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 176   // M-ints have highest priority; consider S-ints only if no M-ints pending
 177   if (enabled_interrupts == 0)
 178     enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
 179
 180   if (state.dcsr.cause == 0 && enabled_interrupts) {
 181     // nonstandard interrupts have highest priority
 182     if (enabled_interrupts >> IRQ_M_EXT)
 183       enabled_interrupts = enabled_interrupts >> IRQ_M_EXT << IRQ_M_EXT;
 184     // external interrupts have next-highest priority
 185     else if (enabled_interrupts & (MIP_MEIP | MIP_SEIP))
 186       enabled_interrupts = enabled_interrupts & (MIP_MEIP | MIP_SEIP);
 187     // software interrupts have next-highest priority
 188     else if (enabled_interrupts & (MIP_MSIP | MIP_SSIP))
 189       enabled_interrupts = enabled_interrupts & (MIP_MSIP | MIP_SSIP);
 190     // timer interrupts have next-highest priority
 191     else if (enabled_interrupts & (MIP_MTIP | MIP_STIP))
 192       enabled_interrupts = enabled_interrupts & (MIP_MTIP | MIP_STIP);
 193     else
 194       abort();
 195
 196     throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
 197   }
 198 }
 199
 200 static int xlen_to_uxl(int xlen)
 201 {
 202   if (xlen == 32)
 203     return 1;
 204   if (xlen == 64)
 205     return 2;
 206   abort();
 207 }
 208
 209 reg_t processor_t::legalize_privilege(reg_t prv)
 210 {
 211   assert(prv <= PRV_M);
 212
 213   if (!supports_extension('U'))
 214     return PRV_M;
 215
 216   if (prv == PRV_H || !supports_extension('S'))
 217     return PRV_U;
 218
 219   return prv;
 220 }
 221
 222 void processor_t::set_privilege(reg_t prv)
 223 {
 224   mmu->flush_tlb();
 225   state.prv = legalize_privilege(prv);
 226 }
 227
 228 void processor_t::enter_debug_mode(uint8_t cause)
 229 {
 230   state.dcsr.cause = cause;
 231   state.dcsr.prv = state.prv;
 232   set_privilege(PRV_M);
 233   state.dpc = state.pc;
 234   state.pc = DEBUG_ROM_ENTRY;
 235 }
 236
 237 void processor_t::take_trap(trap_t& t, reg_t epc)
 238 {
 239   if (debug) {
 240     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 241             id, t.name(), epc);
 242     if (t.has_tval())
 243       fprintf(stderr, "core %3d:           tval 0x%016" PRIx64 "\n", id,
 244           t.get_tval());
 245   }
 246
 247   if (state.dcsr.cause) {
 248     if (t.cause() == CAUSE_BREAKPOINT) {
 249       state.pc = DEBUG_ROM_ENTRY;
 250     } else {
 251       state.pc = DEBUG_ROM_TVEC;
 252     }
 253     return;
 254   }
 255
 256   if (t.cause() == CAUSE_BREAKPOINT && (
 257               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 258               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 259               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 260     enter_debug_mode(DCSR_CAUSE_SWBP);
 261     return;
 262   }
 263
 264   // by default, trap to M-mode, unless delegated to S-mode
 265   reg_t bit = t.cause();
 266   reg_t deleg = state.medeleg;
 267   bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0;
 268   if (interrupt)
 269     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 270   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 271     // handle the trap in S-mode
 272     state.pc = state.stvec;
 273     state.scause = t.cause();
 274     state.sepc = epc;
 275     state.stval = t.get_tval();
 276
 277     reg_t s = state.mstatus;
 278     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
 279     s = set_field(s, MSTATUS_SPP, state.prv);
 280     s = set_field(s, MSTATUS_SIE, 0);
 281     set_csr(CSR_MSTATUS, s);
 282     set_privilege(PRV_S);
 283   } else {
 284     reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0;
 285     state.pc = (state.mtvec & ~(reg_t)1) + vector;
 286     state.mepc = epc;
 287     state.mcause = t.cause();
 288     state.mtval = t.get_tval();
 289
 290     reg_t s = state.mstatus;
 291     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
 292     s = set_field(s, MSTATUS_MPP, state.prv);
 293     s = set_field(s, MSTATUS_MIE, 0);
 294     set_csr(CSR_MSTATUS, s);
 295     set_privilege(PRV_M);
 296   }
 297
 298   yield_load_reservation();
 299 }
 300
 301 void processor_t::disasm(insn_t insn)
 302 {
 303   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 304   if (last_pc != state.pc || last_bits != bits) {
 305     if (executions != 1) {
 306       fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions);
 307     }
 308
 309     fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 310             id, state.pc, bits, disassembler->disassemble(insn).c_str());
 311     last_pc = state.pc;
 312     last_bits = bits;
 313     executions = 1;
 314   } else {
 315     executions++;
 316   }
 317 }
 318
 319 int processor_t::paddr_bits()
 320 {
 321   assert(xlen == max_xlen);
 322   return max_xlen == 64 ? 50 : 34;
 323 }
 324
 325 void processor_t::set_csr(int which, reg_t val)
 326 {
 327   val = zext_xlen(val);
 328   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 329   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 330   switch (which)
 331   {
 332     case CSR_FFLAGS:
 333       dirty_fp_state;
 334       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 335       break;
 336     case CSR_FRM:
 337       dirty_fp_state;
 338       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 339       break;
 340     case CSR_FCSR:
 341       dirty_fp_state;
 342       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 343       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 344       break;
 345     case CSR_MSTATUS: {
 346       if ((val ^ state.mstatus) &
 347           (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR))
 348         mmu->flush_tlb();
 349
 350       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 351                  | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
 352                  | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
 353                  | MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL |
 354                  (ext ? MSTATUS_XS : 0);
 355
 356       reg_t requested_mpp = legalize_privilege(get_field(val, MSTATUS_MPP));
 357       state.mstatus = set_field(state.mstatus, MSTATUS_MPP, requested_mpp);
 358       if (supports_extension('S'))
 359         mask |= MSTATUS_SPP;
 360
 361       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 362
 363       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 364       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 365       if (max_xlen == 32)
 366         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 367       else
 368         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 369
 370       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 371       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 372       state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen));
 373       // U-XLEN == S-XLEN == M-XLEN
 374       xlen = max_xlen;
 375       break;
 376     }
 377     case CSR_MIP: {
 378       reg_t mask = MIP_SSIP | MIP_STIP;
 379       state.mip = (state.mip & ~mask) | (val & mask);
 380       break;
 381     }
 382     case CSR_MIE:
 383       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 384       break;
 385     case CSR_MIDELEG:
 386       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 387       break;
 388     case CSR_MEDELEG: {
 389       reg_t mask =
 390         (1 << CAUSE_MISALIGNED_FETCH) |
 391         (1 << CAUSE_BREAKPOINT) |
 392         (1 << CAUSE_USER_ECALL) |
 393         (1 << CAUSE_FETCH_PAGE_FAULT) |
 394         (1 << CAUSE_LOAD_PAGE_FAULT) |
 395         (1 << CAUSE_STORE_PAGE_FAULT);
 396       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 397       break;
 398     }
 399     case CSR_MINSTRET:
 400     case CSR_MCYCLE:
 401       if (xlen == 32)
 402         state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
 403       else
 404         state.minstret = val;
 405       break;
 406     case CSR_MINSTRETH:
 407     case CSR_MCYCLEH:
 408       state.minstret = (val << 32) | (state.minstret << 32 >> 32);
 409       break;
 410     case CSR_SCOUNTEREN:
 411       state.scounteren = val;
 412       break;
 413     case CSR_MCOUNTEREN:
 414       state.mcounteren = val;
 415       break;
 416     case CSR_SSTATUS: {
 417       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 418                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR;
 419       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 420     }
 421     case CSR_SIP: {
 422       reg_t mask = MIP_SSIP & state.mideleg;
 423       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
 424     }
 425     case CSR_SIE:
 426       return set_csr(CSR_MIE,
 427                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 428     case CSR_SATP: {
 429       mmu->flush_tlb();
 430       if (max_xlen == 32)
 431         state.satp = val & (SATP32_PPN | SATP32_MODE);
 432       if (max_xlen == 64 && (get_field(val, SATP64_MODE) == SATP_MODE_OFF ||
 433                              get_field(val, SATP64_MODE) == SATP_MODE_SV39 ||
 434                              get_field(val, SATP64_MODE) == SATP_MODE_SV48))
 435         state.satp = val & (SATP64_PPN | SATP64_MODE);
 436       break;
 437     }
 438     case CSR_SEPC: state.sepc = val; break;
 439     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 440     case CSR_SSCRATCH: state.sscratch = val; break;
 441     case CSR_SCAUSE: state.scause = val; break;
 442     case CSR_STVAL: state.stval = val; break;
 443     case CSR_MEPC: state.mepc = val; break;
 444     case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break;
 445     case CSR_MSCRATCH: state.mscratch = val; break;
 446     case CSR_MCAUSE: state.mcause = val; break;
 447     case CSR_MTVAL: state.mtval = val; break;
 448     case CSR_MISA: {
 449       if (!(val & (1L << ('F' - 'A'))))
 450         val &= ~(1L << ('D' - 'A'));
 451
 452       // allow MAFDC bits in MISA to be modified
 453       reg_t mask = 0;
 454       mask |= 1L << ('M' - 'A');
 455       mask |= 1L << ('A' - 'A');
 456       mask |= 1L << ('F' - 'A');
 457       mask |= 1L << ('D' - 'A');
 458       mask |= 1L << ('C' - 'A');
 459       mask &= max_isa;
 460
 461       isa = (val & mask) | (isa & ~mask);
 462       break;
 463     }
 464     case CSR_TSELECT:
 465       if (val < state.num_triggers) {
 466         state.tselect = val;
 467       }
 468       break;
 469     case CSR_TDATA1:
 470       {
 471         mcontrol_t *mc = &state.mcontrol[state.tselect];
 472         if (mc->dmode && !state.dcsr.cause) {
 473           break;
 474         }
 475         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
 476         mc->select = get_field(val, MCONTROL_SELECT);
 477         mc->timing = get_field(val, MCONTROL_TIMING);
 478         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 479         mc->chain = get_field(val, MCONTROL_CHAIN);
 480         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 481         mc->m = get_field(val, MCONTROL_M);
 482         mc->h = get_field(val, MCONTROL_H);
 483         mc->s = get_field(val, MCONTROL_S);
 484         mc->u = get_field(val, MCONTROL_U);
 485         mc->execute = get_field(val, MCONTROL_EXECUTE);
 486         mc->store = get_field(val, MCONTROL_STORE);
 487         mc->load = get_field(val, MCONTROL_LOAD);
 488         // Assume we're here because of csrw.
 489         if (mc->execute)
 490           mc->timing = 0;
 491         trigger_updated();
 492       }
 493       break;
 494     case CSR_TDATA2:
 495       if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
 496         break;
 497       }
 498       if (state.tselect < state.num_triggers) {
 499         state.tdata2[state.tselect] = val;
 500       }
 501       break;
 502     case CSR_DCSR:
 503       state.dcsr.prv = get_field(val, DCSR_PRV);
 504       state.dcsr.step = get_field(val, DCSR_STEP);
 505       // TODO: ndreset and fullreset
 506       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 507       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 508       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 509       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 510       state.dcsr.halt = get_field(val, DCSR_HALT);
 511       break;
 512     case CSR_DPC:
 513       state.dpc = val;
 514       break;
 515     case CSR_DSCRATCH:
 516       state.dscratch = val;
 517       break;
 518   }
 519 }
 520
 521 reg_t processor_t::get_csr(int which)
 522 {
 523   uint32_t ctr_en = -1;
 524   if (state.prv < PRV_M)
 525     ctr_en &= state.mcounteren;
 526   if (state.prv < PRV_S)
 527     ctr_en &= state.scounteren;
 528   bool ctr_ok = (ctr_en >> (which & 31)) & 1;
 529
 530   if (ctr_ok) {
 531     if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
 532       return 0;
 533     if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
 534       return 0;
 535   }
 536   if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 537     return 0;
 538   if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H)
 539     return 0;
 540   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
 541     return 0;
 542
 543   switch (which)
 544   {
 545     case CSR_FFLAGS:
 546       require_fp;
 547       if (!supports_extension('F'))
 548         break;
 549       return state.fflags;
 550     case CSR_FRM:
 551       require_fp;
 552       if (!supports_extension('F'))
 553         break;
 554       return state.frm;
 555     case CSR_FCSR:
 556       require_fp;
 557       if (!supports_extension('F'))
 558         break;
 559       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 560     case CSR_INSTRET:
 561     case CSR_CYCLE:
 562       if (ctr_ok)
 563         return state.minstret;
 564       break;
 565     case CSR_MINSTRET:
 566     case CSR_MCYCLE:
 567       return state.minstret;
 568     case CSR_MINSTRETH:
 569     case CSR_MCYCLEH:
 570       if (xlen == 32)
 571         return state.minstret >> 32;
 572       break;
 573     case CSR_SCOUNTEREN: return state.scounteren;
 574     case CSR_MCOUNTEREN: return state.mcounteren;
 575     case CSR_SSTATUS: {
 576       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 577                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_UXL;
 578       reg_t sstatus = state.mstatus & mask;
 579       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 580           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 581         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 582       return sstatus;
 583     }
 584     case CSR_SIP: return state.mip & state.mideleg;
 585     case CSR_SIE: return state.mie & state.mideleg;
 586     case CSR_SEPC: return state.sepc;
 587     case CSR_STVAL: return state.stval;
 588     case CSR_STVEC: return state.stvec;
 589     case CSR_SCAUSE:
 590       if (max_xlen > xlen)
 591         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 592       return state.scause;
 593     case CSR_SATP:
 594       if (get_field(state.mstatus, MSTATUS_TVM))
 595         require_privilege(PRV_M);
 596       return state.satp;
 597     case CSR_SSCRATCH: return state.sscratch;
 598     case CSR_MSTATUS: return state.mstatus;
 599     case CSR_MIP: return state.mip;
 600     case CSR_MIE: return state.mie;
 601     case CSR_MEPC: return state.mepc;
 602     case CSR_MSCRATCH: return state.mscratch;
 603     case CSR_MCAUSE: return state.mcause;
 604     case CSR_MTVAL: return state.mtval;
 605     case CSR_MISA: return isa;
 606     case CSR_MARCHID: return 0;
 607     case CSR_MIMPID: return 0;
 608     case CSR_MVENDORID: return 0;
 609     case CSR_MHARTID: return id;
 610     case CSR_MTVEC: return state.mtvec;
 611     case CSR_MEDELEG: return state.medeleg;
 612     case CSR_MIDELEG: return state.mideleg;
 613     case CSR_TSELECT: return state.tselect;
 614     case CSR_TDATA1:
 615       if (state.tselect < state.num_triggers) {
 616         reg_t v = 0;
 617         mcontrol_t *mc = &state.mcontrol[state.tselect];
 618         v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 619         v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 620         v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 621         v = set_field(v, MCONTROL_SELECT, mc->select);
 622         v = set_field(v, MCONTROL_TIMING, mc->timing);
 623         v = set_field(v, MCONTROL_ACTION, mc->action);
 624         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 625         v = set_field(v, MCONTROL_MATCH, mc->match);
 626         v = set_field(v, MCONTROL_M, mc->m);
 627         v = set_field(v, MCONTROL_H, mc->h);
 628         v = set_field(v, MCONTROL_S, mc->s);
 629         v = set_field(v, MCONTROL_U, mc->u);
 630         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 631         v = set_field(v, MCONTROL_STORE, mc->store);
 632         v = set_field(v, MCONTROL_LOAD, mc->load);
 633         return v;
 634       } else {
 635         return 0;
 636       }
 637       break;
 638     case CSR_TDATA2:
 639       if (state.tselect < state.num_triggers) {
 640         return state.tdata2[state.tselect];
 641       } else {
 642         return 0;
 643       }
 644       break;
 645     case CSR_TDATA3: return 0;
 646     case CSR_DCSR:
 647       {
 648         uint32_t v = 0;
 649         v = set_field(v, DCSR_XDEBUGVER, 1);
 650         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 651         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 652         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 653         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 654         v = set_field(v, DCSR_STOPCYCLE, 0);
 655         v = set_field(v, DCSR_STOPTIME, 0);
 656         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 657         v = set_field(v, DCSR_STEP, state.dcsr.step);
 658         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 659         return v;
 660       }
 661     case CSR_DPC:
 662       return state.dpc;
 663     case CSR_DSCRATCH:
 664       return state.dscratch;
 665   }
 666   throw trap_illegal_instruction(0);
 667 }
 668
 669 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 670 {
 671   throw trap_illegal_instruction(0);
 672 }
 673
 674 insn_func_t processor_t::decode_insn(insn_t insn)
 675 {
 676   // look up opcode in hash table
 677   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 678   insn_desc_t desc = opcode_cache[idx];
 679
 680   if (unlikely(insn.bits() != desc.match)) {
 681     // fall back to linear search
 682     insn_desc_t* p = &instructions[0];
 683     while ((insn.bits() & p->mask) != p->match)
 684       p++;
 685     desc = *p;
 686
 687     if (p->mask != 0 && p > &instructions[0]) {
 688       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 689         // move to front of opcode list to reduce miss penalty
 690         while (--p >= &instructions[0])
 691           *(p+1) = *p;
 692         instructions[0] = desc;
 693       }
 694     }
 695
 696     opcode_cache[idx] = desc;
 697     opcode_cache[idx].match = insn.bits();
 698   }
 699
 700   return xlen == 64 ? desc.rv64 : desc.rv32;
 701 }
 702
 703 void processor_t::register_insn(insn_desc_t desc)
 704 {
 705   instructions.push_back(desc);
 706 }
 707
 708 void processor_t::build_opcode_map()
 709 {
 710   struct cmp {
 711     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 712       if (lhs.match == rhs.match)
 713         return lhs.mask > rhs.mask;
 714       return lhs.match > rhs.match;
 715     }
 716   };
 717   std::sort(instructions.begin(), instructions.end(), cmp());
 718
 719   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 720     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 721 }
 722
 723 void processor_t::register_extension(extension_t* x)
 724 {
 725   for (auto insn : x->get_instructions())
 726     register_insn(insn);
 727   build_opcode_map();
 728   for (auto disasm_insn : x->get_disasms())
 729     disassembler->add_insn(disasm_insn);
 730   if (ext != NULL)
 731     throw std::logic_error("only one extension may be registered");
 732   ext = x;
 733   x->set_processor(this);
 734 }
 735
 736 void processor_t::register_base_instructions()
 737 {
 738   #define DECLARE_INSN(name, match, mask) \
 739     insn_bits_t name##_match = (match), name##_mask = (mask);
 740   #include "encoding.h"
 741   #undef DECLARE_INSN
 742
 743   #define DEFINE_INSN(name) \
 744     REGISTER_INSN(this, name, name##_match, name##_mask)
 745   #include "insn_list.h"
 746   #undef DEFINE_INSN
 747
 748   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 749   build_opcode_map();
 750 }
 751
 752 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 753 {
 754   switch (addr)
 755   {
 756     case 0:
 757       if (len <= 4) {
 758         memset(bytes, 0, len);
 759         bytes[0] = get_field(state.mip, MIP_MSIP);
 760         return true;
 761       }
 762       break;
 763   }
 764
 765   return false;
 766 }
 767
 768 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 769 {
 770   switch (addr)
 771   {
 772     case 0:
 773       if (len <= 4) {
 774         state.mip = set_field(state.mip, MIP_MSIP, bytes[0]);
 775         return true;
 776       }
 777       break;
 778   }
 779
 780   return false;
 781 }
 782
 783 void processor_t::trigger_updated()
 784 {
 785   mmu->flush_tlb();
 786   mmu->check_triggers_fetch = false;
 787   mmu->check_triggers_load = false;
 788   mmu->check_triggers_store = false;
 789
 790   for (unsigned i = 0; i < state.num_triggers; i++) {
 791     if (state.mcontrol[i].execute) {
 792       mmu->check_triggers_fetch = true;
 793     }
 794     if (state.mcontrol[i].load) {
 795       mmu->check_triggers_load = true;
 796     }
 797     if (state.mcontrol[i].store) {
 798       mmu->check_triggers_store = true;
 799     }
 800   }
 801 }