riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "htif.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
  23   : sim(sim), ext(NULL), disassembler(new disassembler_t),
  24     id(id), run(false), debug(false)
  25 {
  26   parse_isa_string(isa);
  27
  28   mmu = new mmu_t(sim->mem, sim->memsz);
  29   mmu->set_processor(this);
  30
  31   reset(true);
  32
  33   #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
  34   #include "encoding.h"
  35   #undef DECLARE_INSN
  36   build_opcode_map();
  37 }
  38
  39 processor_t::~processor_t()
  40 {
  41 #ifdef RISCV_ENABLE_HISTOGRAM
  42   if (histogram_enabled)
  43   {
  44     fprintf(stderr, "PC Histogram size:%lu\n", pc_histogram.size());
  45     for(auto iterator = pc_histogram.begin(); iterator != pc_histogram.end(); ++iterator) {
  46       fprintf(stderr, "%0lx %lu\n", (iterator->first << 2), iterator->second);
  47     }
  48   }
  49 #endif
  50
  51   delete mmu;
  52   delete disassembler;
  53 }
  54
  55 static void bad_isa_string(const char* isa)
  56 {
  57   fprintf(stderr, "error: bad --isa option %s\n", isa);
  58   abort();
  59 }
  60
  61 void processor_t::parse_isa_string(const char* isa)
  62 {
  63   const char* p = isa;
  64   const char* all_subsets = "IMAFDC";
  65
  66   max_xlen = 64;
  67   cpuid = reg_t(2) << 62;
  68
  69   if (strncmp(p, "RV32", 4) == 0)
  70     max_xlen = 32, cpuid = 0, p += 4;
  71   else if (strncmp(p, "RV64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "RV", 2) == 0)
  74     p += 2;
  75
  76   cpuid |= 1L << ('S' - 'A'); // advertise support for supervisor mode
  77
  78   if (!*p)
  79     p = all_subsets;
  80   else if (*p != 'I')
  81     bad_isa_string(isa);
  82
  83   while (*p) {
  84     cpuid |= 1L << (*p - 'A');
  85
  86     if (auto next = strchr(all_subsets, *p)) {
  87       all_subsets = next + 1;
  88       p++;
  89     } else if (*p == 'X') {
  90       const char* ext = p+1, *end = ext;
  91       while (islower(*end))
  92         end++;
  93       register_extension(find_extension(std::string(ext, end - ext).c_str())());
  94       p = end;
  95     } else {
  96       bad_isa_string(isa);
  97     }
  98   }
  99
 100   if (supports_extension('D') && !supports_extension('F'))
 101     bad_isa_string(isa);
 102 }
 103
 104 void state_t::reset()
 105 {
 106   memset(this, 0, sizeof(*this));
 107   mstatus = set_field(mstatus, MSTATUS_PRV, PRV_M);
 108   mstatus = set_field(mstatus, MSTATUS_PRV1, PRV_S);
 109   mstatus = set_field(mstatus, MSTATUS_PRV2, PRV_S);
 110   pc = DEFAULT_MTVEC + 0x100;
 111   load_reservation = -1;
 112 }
 113
 114 void processor_t::set_debug(bool value)
 115 {
 116   debug = value;
 117   if (ext)
 118     ext->set_debug(value);
 119 }
 120
 121 void processor_t::set_histogram(bool value)
 122 {
 123   histogram_enabled = value;
 124 #ifndef RISCV_ENABLE_HISTOGRAM
 125   if (value) {
 126     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 127     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 128   }
 129 #endif
 130 }
 131
 132 void processor_t::reset(bool value)
 133 {
 134   if (run == !value)
 135     return;
 136   run = !value;
 137
 138   state.reset();
 139   set_csr(CSR_MSTATUS, state.mstatus);
 140
 141   if (ext)
 142     ext->reset(); // reset the extension
 143 }
 144
 145 void processor_t::raise_interrupt(reg_t which)
 146 {
 147   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 148 }
 149
 150 void processor_t::take_interrupt()
 151 {
 152   int priv = get_field(state.mstatus, MSTATUS_PRV);
 153   int ie = get_field(state.mstatus, MSTATUS_IE);
 154   reg_t interrupts = state.mie & state.mip;
 155
 156   if (priv < PRV_M || (priv == PRV_M && ie)) {
 157     if (interrupts & MIP_MSIP)
 158       raise_interrupt(IRQ_SOFT);
 159
 160     if (interrupts & MIP_MTIP)
 161       raise_interrupt(IRQ_TIMER);
 162
 163     if (state.fromhost != 0)
 164       raise_interrupt(IRQ_HOST);
 165   }
 166
 167   if (priv < PRV_S || (priv == PRV_S && ie)) {
 168     if (interrupts & MIP_SSIP)
 169       raise_interrupt(IRQ_SOFT);
 170
 171     if (interrupts & MIP_STIP)
 172       raise_interrupt(IRQ_TIMER);
 173   }
 174 }
 175
 176 static void commit_log(state_t* state, reg_t pc, insn_t insn)
 177 {
 178 #ifdef RISCV_ENABLE_COMMITLOG
 179   if (get_field(state->mstatus, MSTATUS_IE)) {
 180     uint64_t mask = (insn.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn.length() * 8))) - 1;
 181     if (state->log_reg_write.addr) {
 182       fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ") %c%2" PRIu64 " 0x%016" PRIx64 "\n",
 183               pc,
 184               insn.bits() & mask,
 185               state->log_reg_write.addr & 1 ? 'f' : 'x',
 186               state->log_reg_write.addr >> 1,
 187               state->log_reg_write.data);
 188     } else {
 189       fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ")\n", pc, insn.bits() & mask);
 190     }
 191   }
 192   state->log_reg_write.addr = 0;
 193 #endif
 194 }
 195
 196 inline void processor_t::update_histogram(size_t pc)
 197 {
 198 #ifdef RISCV_ENABLE_HISTOGRAM
 199   size_t idx = pc >> 2;
 200   pc_histogram[idx]++;
 201 #endif
 202 }
 203
 204 static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
 205 {
 206   reg_t npc = fetch.func(p, fetch.insn, pc);
 207   if (npc != PC_SERIALIZE) {
 208     commit_log(p->get_state(), pc, fetch.insn);
 209     p->update_histogram(pc);
 210   }
 211   return npc;
 212 }
 213
 214 void processor_t::check_timer()
 215 {
 216   if (sim->rtc >= state.mtimecmp)
 217     state.mip |= MIP_MTIP;
 218 }
 219
 220 void processor_t::step(size_t n)
 221 {
 222   size_t instret = 0;
 223   reg_t pc = state.pc;
 224   mmu_t* _mmu = mmu;
 225
 226   if (unlikely(!run || !n))
 227     return;
 228
 229   #define maybe_serialize() \
 230    if (unlikely(pc == PC_SERIALIZE)) { \
 231      pc = state.pc; \
 232      state.serialized = true; \
 233      break; \
 234    }
 235
 236   try
 237   {
 238     check_timer();
 239     take_interrupt();
 240
 241     if (unlikely(debug))
 242     {
 243       while (instret < n)
 244       {
 245         insn_fetch_t fetch = mmu->load_insn(pc);
 246         if (!state.serialized)
 247           disasm(fetch.insn);
 248         pc = execute_insn(this, pc, fetch);
 249         maybe_serialize();
 250         instret++;
 251         state.pc = pc;
 252       }
 253     }
 254     else while (instret < n)
 255     {
 256       size_t idx = _mmu->icache_index(pc);
 257       auto ic_entry = _mmu->access_icache(pc);
 258
 259       #define ICACHE_ACCESS(idx) { \
 260         insn_fetch_t fetch = ic_entry->data; \
 261         ic_entry++; \
 262         pc = execute_insn(this, pc, fetch); \
 263         if (idx == mmu_t::ICACHE_ENTRIES-1) break; \
 264         if (unlikely(ic_entry->tag != pc)) break; \
 265         if (unlikely(instret+1 == n)) break; \
 266         instret++; \
 267         state.pc = pc; \
 268       }
 269
 270       switch (idx) {
 271         #include "icache.h"
 272       }
 273
 274       maybe_serialize();
 275       instret++;
 276       state.pc = pc;
 277     }
 278   }
 279   catch(trap_t& t)
 280   {
 281     take_trap(t, pc);
 282   }
 283
 284   state.minstret += instret;
 285
 286   // tail-recurse if we didn't execute as many instructions as we'd hoped
 287   if (instret < n)
 288     step(n - instret);
 289 }
 290
 291 void processor_t::push_privilege_stack()
 292 {
 293   reg_t s = state.mstatus;
 294   s = set_field(s, MSTATUS_PRV2, get_field(state.mstatus, MSTATUS_PRV1));
 295   s = set_field(s, MSTATUS_IE2, get_field(state.mstatus, MSTATUS_IE1));
 296   s = set_field(s, MSTATUS_PRV1, get_field(state.mstatus, MSTATUS_PRV));
 297   s = set_field(s, MSTATUS_IE1, get_field(state.mstatus, MSTATUS_IE));
 298   s = set_field(s, MSTATUS_PRV, PRV_M);
 299   s = set_field(s, MSTATUS_MPRV, 0);
 300   s = set_field(s, MSTATUS_IE, 0);
 301   set_csr(CSR_MSTATUS, s);
 302 }
 303
 304 void processor_t::pop_privilege_stack()
 305 {
 306   reg_t s = state.mstatus;
 307   s = set_field(s, MSTATUS_PRV, get_field(state.mstatus, MSTATUS_PRV1));
 308   s = set_field(s, MSTATUS_IE, get_field(state.mstatus, MSTATUS_IE1));
 309   s = set_field(s, MSTATUS_PRV1, get_field(state.mstatus, MSTATUS_PRV2));
 310   s = set_field(s, MSTATUS_IE1, get_field(state.mstatus, MSTATUS_IE2));
 311   s = set_field(s, MSTATUS_PRV2, PRV_U);
 312   s = set_field(s, MSTATUS_IE2, 1);
 313   set_csr(CSR_MSTATUS, s);
 314 }
 315
 316 void processor_t::take_trap(trap_t& t, reg_t epc)
 317 {
 318   if (debug)
 319     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 320             id, t.name(), epc);
 321
 322   state.pc = DEFAULT_MTVEC + 0x40 * get_field(state.mstatus, MSTATUS_PRV);
 323   push_privilege_stack();
 324   yield_load_reservation();
 325   state.mcause = t.cause();
 326   state.mepc = epc;
 327   t.side_effects(&state); // might set badvaddr etc.
 328 }
 329
 330 void processor_t::deliver_ipi()
 331 {
 332   state.mip |= MIP_MSIP;
 333 }
 334
 335 void processor_t::disasm(insn_t insn)
 336 {
 337   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 338   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 339           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 340 }
 341
 342 static bool validate_priv(reg_t priv)
 343 {
 344   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 345 }
 346
 347 static bool validate_vm(int max_xlen, reg_t vm)
 348 {
 349   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 350     return true;
 351   if (max_xlen == 32 && vm == VM_SV32)
 352     return true;
 353   return vm == VM_MBARE;
 354 }
 355
 356 void processor_t::set_csr(int which, reg_t val)
 357 {
 358   switch (which)
 359   {
 360     case CSR_FFLAGS:
 361       dirty_fp_state;
 362       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 363       break;
 364     case CSR_FRM:
 365       dirty_fp_state;
 366       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 367       break;
 368     case CSR_FCSR:
 369       dirty_fp_state;
 370       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 371       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 372       break;
 373     case CSR_MTIME:
 374     case CSR_STIMEW:
 375       // this implementation ignores writes to MTIME
 376       break;
 377     case CSR_MTIMEH:
 378     case CSR_STIMEHW:
 379       // this implementation ignores writes to MTIME
 380       break;
 381     case CSR_TIMEW:
 382       val -= sim->rtc;
 383       if (xlen == 32)
 384         state.sutime_delta = (uint32_t)val | (state.sutime_delta >> 32 << 32);
 385       else
 386         state.sutime_delta = val;
 387       break;
 388     case CSR_TIMEHW:
 389       val = ((val << 32) - sim->rtc) >> 32;
 390       state.sutime_delta = (val << 32) | (uint32_t)state.sutime_delta;
 391       break;
 392     case CSR_CYCLEW:
 393     case CSR_INSTRETW:
 394       val -= state.minstret;
 395       if (xlen == 32)
 396         state.suinstret_delta = (uint32_t)val | (state.suinstret_delta >> 32 << 32);
 397       else
 398         state.suinstret_delta = val;
 399       break;
 400     case CSR_CYCLEHW:
 401     case CSR_INSTRETHW:
 402       val = ((val << 32) - state.minstret) >> 32;
 403       state.suinstret_delta = (val << 32) | (uint32_t)state.suinstret_delta;
 404       break;
 405     case CSR_MSTATUS: {
 406       if ((val ^ state.mstatus) & (MSTATUS_VM | MSTATUS_PRV | MSTATUS_PRV1 | MSTATUS_MPRV))
 407         mmu->flush_tlb();
 408
 409       reg_t mask = MSTATUS_IE | MSTATUS_IE1 | MSTATUS_IE2 | MSTATUS_MPRV
 410                    | MSTATUS_FS | (ext ? MSTATUS_XS : 0);
 411
 412       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 413         mask |= MSTATUS_VM;
 414       if (validate_priv(get_field(val, MSTATUS_PRV)))
 415         mask |= MSTATUS_PRV;
 416       if (validate_priv(get_field(val, MSTATUS_PRV1)))
 417         mask |= MSTATUS_PRV1;
 418       if (validate_priv(get_field(val, MSTATUS_PRV2)))
 419         mask |= MSTATUS_PRV2;
 420
 421       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 422
 423       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 424       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 425       if (max_xlen == 32)
 426         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 427       else
 428         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 429
 430       // spike supports the notion of xlen < max_xlen, but current priv spec
 431       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 432       xlen = max_xlen;
 433       break;
 434     }
 435     case CSR_MIP: {
 436       reg_t mask = MIP_SSIP | MIP_MSIP | MIP_STIP;
 437       state.mip = (state.mip & ~mask) | (val & mask);
 438       break;
 439     }
 440     case CSR_MIE: {
 441       reg_t mask = MIP_SSIP | MIP_MSIP | MIP_STIP | MIP_MTIP;
 442       state.mie = (state.mie & ~mask) | (val & mask);
 443       break;
 444     }
 445     case CSR_SSTATUS: {
 446       reg_t ms = state.mstatus;
 447       ms = set_field(ms, MSTATUS_IE, get_field(val, SSTATUS_IE));
 448       ms = set_field(ms, MSTATUS_IE1, get_field(val, SSTATUS_PIE));
 449       ms = set_field(ms, MSTATUS_PRV1, get_field(val, SSTATUS_PS));
 450       ms = set_field(ms, MSTATUS_FS, get_field(val, SSTATUS_FS));
 451       ms = set_field(ms, MSTATUS_XS, get_field(val, SSTATUS_XS));
 452       ms = set_field(ms, MSTATUS_MPRV, get_field(val, SSTATUS_MPRV));
 453       return set_csr(CSR_MSTATUS, ms);
 454     }
 455     case CSR_SIP: {
 456       reg_t mask = MIP_SSIP;
 457       state.mip = (state.mip & ~mask) | (val & mask);
 458       break;
 459     }
 460     case CSR_SIE: {
 461       reg_t mask = MIP_SSIP | MIP_STIP;
 462       state.mie = (state.mie & ~mask) | (val & mask);
 463       break;
 464     }
 465     case CSR_SEPC: state.sepc = val; break;
 466     case CSR_STVEC: state.stvec = val & ~3; break;
 467     case CSR_SPTBR: state.sptbr = zext_xlen(val & -PGSIZE); break;
 468     case CSR_SSCRATCH: state.sscratch = val; break;
 469     case CSR_MEPC: state.mepc = val; break;
 470     case CSR_MSCRATCH: state.mscratch = val; break;
 471     case CSR_MCAUSE: state.mcause = val; break;
 472     case CSR_MBADADDR: state.mbadaddr = val; break;
 473     case CSR_MTIMECMP:
 474       state.mip &= ~MIP_MTIP;
 475       state.mtimecmp = val;
 476       break;
 477     case CSR_SEND_IPI: sim->send_ipi(val); break;
 478     case CSR_MTOHOST:
 479       if (state.tohost == 0)
 480         state.tohost = val;
 481       break;
 482     case CSR_MFROMHOST: state.fromhost = val; break;
 483   }
 484 }
 485
 486 reg_t processor_t::get_csr(int which)
 487 {
 488   switch (which)
 489   {
 490     case CSR_FFLAGS:
 491       require_fp;
 492       if (!supports_extension('F'))
 493         break;
 494       return state.fflags;
 495     case CSR_FRM:
 496       require_fp;
 497       if (!supports_extension('F'))
 498         break;
 499       return state.frm;
 500     case CSR_FCSR:
 501       require_fp;
 502       if (!supports_extension('F'))
 503         break;
 504       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 505     case CSR_MTIME:
 506     case CSR_STIME:
 507     case CSR_STIMEW:
 508       return sim->rtc;
 509     case CSR_MTIMEH:
 510     case CSR_STIMEH:
 511     case CSR_STIMEHW:
 512       return sim->rtc >> 32;
 513     case CSR_TIME:
 514     case CSR_TIMEW:
 515       return sim->rtc + state.sutime_delta;
 516     case CSR_CYCLE:
 517     case CSR_CYCLEW:
 518     case CSR_INSTRET:
 519     case CSR_INSTRETW:
 520       return state.minstret + state.suinstret_delta;
 521     case CSR_TIMEH:
 522     case CSR_TIMEHW:
 523       if (xlen == 64)
 524         break;
 525       return (sim->rtc + state.sutime_delta) >> 32;
 526     case CSR_CYCLEH:
 527     case CSR_INSTRETH:
 528     case CSR_CYCLEHW:
 529     case CSR_INSTRETHW:
 530       if (xlen == 64)
 531         break;
 532       return (state.minstret + state.suinstret_delta) >> 32;
 533     case CSR_SSTATUS: {
 534       reg_t ss = 0;
 535       ss = set_field(ss, SSTATUS_IE, get_field(state.mstatus, MSTATUS_IE));
 536       ss = set_field(ss, SSTATUS_PIE, get_field(state.mstatus, MSTATUS_IE1));
 537       ss = set_field(ss, SSTATUS_PS, get_field(state.mstatus, MSTATUS_PRV1));
 538       ss = set_field(ss, SSTATUS_FS, get_field(state.mstatus, MSTATUS_FS));
 539       ss = set_field(ss, SSTATUS_XS, get_field(state.mstatus, MSTATUS_XS));
 540       ss = set_field(ss, SSTATUS_MPRV, get_field(state.mstatus, MSTATUS_MPRV));
 541       if (get_field(state.mstatus, MSTATUS64_SD))
 542         ss = set_field(ss, (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD), 1);
 543       return ss;
 544     }
 545     case CSR_SIP: return state.mip & (MIP_SSIP | MIP_STIP);
 546     case CSR_SIE: return state.mie & (MIP_SSIP | MIP_STIP);
 547     case CSR_SEPC: return state.sepc;
 548     case CSR_SBADADDR: return state.sbadaddr;
 549     case CSR_STVEC: return state.stvec;
 550     case CSR_SCAUSE:
 551       if (max_xlen > xlen)
 552         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 553       return state.scause;
 554     case CSR_SPTBR: return state.sptbr;
 555     case CSR_SASID: return 0;
 556     case CSR_SSCRATCH: return state.sscratch;
 557     case CSR_MSTATUS: return state.mstatus;
 558     case CSR_MIP: return state.mip;
 559     case CSR_MIE: return state.mie;
 560     case CSR_MEPC: return state.mepc;
 561     case CSR_MSCRATCH: return state.mscratch;
 562     case CSR_MCAUSE: return state.mcause;
 563     case CSR_MBADADDR: return state.mbadaddr;
 564     case CSR_MTIMECMP: return state.mtimecmp;
 565     case CSR_MCPUID: return cpuid;
 566     case CSR_MIMPID: return IMPL_ROCKET;
 567     case CSR_MHARTID: return id;
 568     case CSR_MTVEC: return DEFAULT_MTVEC;
 569     case CSR_MTDELEG: return 0;
 570     case CSR_MTOHOST:
 571       sim->get_htif()->tick(); // not necessary, but faster
 572       return state.tohost;
 573     case CSR_MFROMHOST:
 574       sim->get_htif()->tick(); // not necessary, but faster
 575       return state.fromhost;
 576     case CSR_SEND_IPI: return 0;
 577     case CSR_UARCH0:
 578     case CSR_UARCH1:
 579     case CSR_UARCH2:
 580     case CSR_UARCH3:
 581     case CSR_UARCH4:
 582     case CSR_UARCH5:
 583     case CSR_UARCH6:
 584     case CSR_UARCH7:
 585     case CSR_UARCH8:
 586     case CSR_UARCH9:
 587     case CSR_UARCH10:
 588     case CSR_UARCH11:
 589     case CSR_UARCH12:
 590     case CSR_UARCH13:
 591     case CSR_UARCH14:
 592     case CSR_UARCH15:
 593       return 0;
 594   }
 595   throw trap_illegal_instruction();
 596 }
 597
 598 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 599 {
 600   throw trap_illegal_instruction();
 601 }
 602
 603 insn_func_t processor_t::decode_insn(insn_t insn)
 604 {
 605   size_t mask = opcode_map.size()-1;
 606   insn_desc_t* desc = opcode_map[insn.bits() & mask];
 607
 608   while ((insn.bits() & desc->mask) != desc->match)
 609     desc++;
 610
 611   return xlen == 64 ? desc->rv64 : desc->rv32;
 612 }
 613
 614 void processor_t::register_insn(insn_desc_t desc)
 615 {
 616   assert(desc.mask & 1);
 617   instructions.push_back(desc);
 618 }
 619
 620 void processor_t::build_opcode_map()
 621 {
 622   size_t buckets = -1;
 623   for (auto& inst : instructions)
 624     while ((inst.mask & buckets) != buckets)
 625       buckets /= 2;
 626   buckets++;
 627
 628   struct cmp {
 629     decltype(insn_desc_t::match) mask;
 630     cmp(decltype(mask) mask) : mask(mask) {}
 631     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 632       if ((lhs.match & mask) != (rhs.match & mask))
 633         return (lhs.match & mask) < (rhs.match & mask);
 634       return lhs.match < rhs.match;
 635     }
 636   };
 637   std::sort(instructions.begin(), instructions.end(), cmp(buckets-1));
 638
 639   opcode_map.resize(buckets);
 640   opcode_store.resize(instructions.size() + 1);
 641
 642   size_t j = 0;
 643   for (size_t b = 0, i = 0; b < buckets; b++)
 644   {
 645     opcode_map[b] = &opcode_store[j];
 646     while (i < instructions.size() && b == (instructions[i].match & (buckets-1)))
 647       opcode_store[j++] = instructions[i++];
 648   }
 649
 650   assert(j == opcode_store.size()-1);
 651   opcode_store[j].match = opcode_store[j].mask = 0;
 652   opcode_store[j].rv32 = &illegal_instruction;
 653   opcode_store[j].rv64 = &illegal_instruction;
 654 }
 655
 656 void processor_t::register_extension(extension_t* x)
 657 {
 658   for (auto insn : x->get_instructions())
 659     register_insn(insn);
 660   build_opcode_map();
 661   for (auto disasm_insn : x->get_disasms())
 662     disassembler->add_insn(disasm_insn);
 663   if (ext != NULL)
 664     throw std::logic_error("only one extension may be registered");
 665   ext = x;
 666   x->set_processor(this);
 667 }