riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "disasm.h"
   9 #include <cinttypes>
  10 #include <cmath>
  11 #include <cstdlib>
  12 #include <iostream>
  13 #include <assert.h>
  14 #include <limits.h>
  15 #include <stdexcept>
  16
  17 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
  18   : sim(_sim), mmu(_mmu), ext(NULL), id(_id), opcode_bits(0)
  19 {
  20   reset(true);
  21   mmu->set_processor(this);
  22
  23   #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
  24   #include "opcodes.h"
  25   #undef DECLARE_INSN
  26 }
  27
  28 processor_t::~processor_t()
  29 {
  30 }
  31
  32 void state_t::reset()
  33 {
  34   // the ISA guarantees on boot that the PC is 0x2000 and the the processor
  35   // is in supervisor mode, and in 64-bit mode, if supported, with traps
  36   // and virtual memory disabled.
  37   sr = SR_S;
  38 #ifdef RISCV_ENABLE_64BIT
  39   sr |= SR_S64;
  40 #endif
  41   pc = 0x2000;
  42
  43   // the following state is undefined upon boot-up,
  44   // but we zero it for determinism
  45   XPR.reset();
  46   FPR.reset();
  47
  48   evec = 0;
  49   epc = 0;
  50   badvaddr = 0;
  51   cause = 0;
  52   pcr_k0 = 0;
  53   pcr_k1 = 0;
  54   count = 0;
  55   compare = 0;
  56   cycle = 0;
  57   fsr = 0;
  58
  59   load_reservation = -1;
  60 }
  61
  62 void processor_t::reset(bool value)
  63 {
  64   if (run == !value)
  65     return;
  66   run = !value;
  67
  68   state.reset();
  69 }
  70
  71 uint32_t processor_t::set_fsr(uint32_t val)
  72 {
  73   uint32_t old_fsr = state.fsr;
  74   state.fsr = val & ~FSR_ZERO; // clear FSR bits that read as zero
  75   return old_fsr;
  76 }
  77
  78 void processor_t::take_interrupt()
  79 {
  80   uint32_t interrupts = (state.sr & SR_IP) >> SR_IP_SHIFT;
  81   interrupts &= (state.sr & SR_IM) >> SR_IM_SHIFT;
  82
  83   if (interrupts && (state.sr & SR_EI))
  84     for (int i = 0; ; i++, interrupts >>= 1)
  85       if (interrupts & 1)
  86         throw trap_t((1ULL << ((state.sr & SR_S64) ? 63 : 31)) + i);
  87 }
  88
  89 void processor_t::step(size_t n, bool noisy)
  90 {
  91   if(!run)
  92     return;
  93
  94   size_t i = 0;
  95   reg_t npc = state.pc;
  96   mmu_t* _mmu = mmu;
  97
  98   try
  99   {
 100     take_interrupt();
 101
 102     // execute_insn fetches and executes one instruction
 103     #define execute_insn(noisy) \
 104       do { \
 105         mmu_t::insn_fetch_t fetch = _mmu->load_insn(npc); \
 106         if(noisy) disasm(fetch.insn.insn, npc); \
 107         npc = fetch.func(this, fetch.insn.insn, npc); \
 108       } while(0)
 109
 110
 111     // special execute_insn  for commit log dumping
 112 #ifdef RISCV_ENABLE_COMMITLOG
 113     //static disassembler disasmblr;
 114     #undef execute_insn
 115     #define execute_insn(noisy) \
 116       do { \
 117         mmu_t::insn_fetch_t fetch = _mmu->load_insn(npc); \
 118         if(noisy) disasm(fetch.insn.insn, npc); \
 119         bool in_spvr = state.sr & SR_S; \
 120         if (!in_spvr) fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") ", npc, fetch.insn.insn.bits()); \
 121         /*if (!in_spvr) fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") %s  ", npc, fetch.insn.insn.bits(), disasmblr.disassemble(fetch.insn.insn).c_str());*/ \
 122         npc = fetch.func(this, fetch.insn.insn, npc); \
 123       } while(0)
 124 #endif
 125
 126     if(noisy) for( ; i < n; i++) // print out instructions as we go
 127       execute_insn(true);
 128     else
 129     {
 130       // unrolled for speed
 131       for( ; n > 3 && i < n-3; i+=4)
 132       {
 133         execute_insn(false);
 134         execute_insn(false);
 135         execute_insn(false);
 136         execute_insn(false);
 137       }
 138       for( ; i < n; i++)
 139         execute_insn(false);
 140     }
 141
 142     state.pc = npc;
 143   }
 144   catch(trap_t& t)
 145   {
 146     take_trap(npc, t, noisy);
 147   }
 148
 149   state.cycle += i;
 150
 151   // update timer and possibly register a timer interrupt
 152   uint32_t old_count = state.count;
 153   state.count += i;
 154   if(old_count < state.compare && uint64_t(old_count) + i >= state.compare)
 155     set_interrupt(IRQ_TIMER, true);
 156 }
 157
 158 void processor_t::take_trap(reg_t pc, trap_t& t, bool noisy)
 159 {
 160   if (noisy)
 161     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 162             id, t.name(), pc);
 163
 164   // switch to supervisor, set previous supervisor bit, disable interrupts
 165   set_pcr(PCR_SR, (((state.sr & ~SR_EI) | SR_S) & ~SR_PS & ~SR_PEI) |
 166                   ((state.sr & SR_S) ? SR_PS : 0) |
 167                   ((state.sr & SR_EI) ? SR_PEI : 0));
 168
 169   yield_load_reservation();
 170   state.cause = t.cause();
 171   state.epc = pc;
 172   state.pc = state.evec;
 173
 174   t.side_effects(&state); // might set badvaddr etc.
 175 }
 176
 177 void processor_t::deliver_ipi()
 178 {
 179   if (run)
 180     set_pcr(PCR_CLR_IPI, 1);
 181 }
 182
 183 void processor_t::disasm(insn_t insn, reg_t pc)
 184 {
 185   // the disassembler is stateless, so we share it
 186   static disassembler disasm;
 187   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx32 ") %s\n",
 188           id, state.pc, insn.bits(), disasm.disassemble(insn).c_str());
 189 }
 190
 191 reg_t processor_t::set_pcr(int which, reg_t val)
 192 {
 193   reg_t old_pcr = get_pcr(which);
 194
 195   switch (which)
 196   {
 197     case PCR_SR:
 198       state.sr = (val & ~SR_IP) | (state.sr & SR_IP);
 199 #ifndef RISCV_ENABLE_64BIT
 200       state.sr &= ~(SR_S64 | SR_U64);
 201 #endif
 202 #ifndef RISCV_ENABLE_FPU
 203       state.sr &= ~SR_EF;
 204 #endif
 205 #ifndef RISCV_ENABLE_VEC
 206       state.sr &= ~SR_EV;
 207 #endif
 208       state.sr &= ~SR_ZERO;
 209       mmu->flush_tlb();
 210       break;
 211     case PCR_EPC:
 212       state.epc = val;
 213       break;
 214     case PCR_EVEC:
 215       state.evec = val;
 216       break;
 217     case PCR_COUNT:
 218       state.count = val;
 219       break;
 220     case PCR_COMPARE:
 221       set_interrupt(IRQ_TIMER, false);
 222       state.compare = val;
 223       break;
 224     case PCR_PTBR:
 225       state.ptbr = val & ~(PGSIZE-1);
 226       break;
 227     case PCR_SEND_IPI:
 228       sim->send_ipi(val);
 229       break;
 230     case PCR_CLR_IPI:
 231       set_interrupt(IRQ_IPI, val & 1);
 232       break;
 233     case PCR_SUP0:
 234       state.pcr_k0 = val;
 235       break;
 236     case PCR_SUP1:
 237       state.pcr_k1 = val;
 238       break;
 239     case PCR_TOHOST:
 240       if (state.tohost == 0)
 241         state.tohost = val;
 242       break;
 243     case PCR_FROMHOST:
 244       set_interrupt(IRQ_HOST, val != 0);
 245       state.fromhost = val;
 246       break;
 247   }
 248
 249   return old_pcr;
 250 }
 251
 252 reg_t processor_t::get_pcr(int which)
 253 {
 254   switch (which)
 255   {
 256     case PCR_SR:
 257       return state.sr;
 258     case PCR_EPC:
 259       return state.epc;
 260     case PCR_BADVADDR:
 261       return state.badvaddr;
 262     case PCR_EVEC:
 263       return state.evec;
 264     case PCR_COUNT:
 265       return state.count;
 266     case PCR_COMPARE:
 267       return state.compare;
 268     case PCR_CAUSE:
 269       return state.cause;
 270     case PCR_PTBR:
 271       return state.ptbr;
 272     case PCR_ASID:
 273       return 0;
 274     case PCR_FATC:
 275       mmu->flush_tlb();
 276       return 0;
 277     case PCR_HARTID:
 278       return id;
 279     case PCR_IMPL:
 280       return 1;
 281     case PCR_SUP0:
 282       return state.pcr_k0;
 283     case PCR_SUP1:
 284       return state.pcr_k1;
 285     case PCR_TOHOST:
 286       return state.tohost;
 287     case PCR_FROMHOST:
 288       return state.fromhost;
 289   }
 290   return -1;
 291 }
 292
 293 void processor_t::set_interrupt(int which, bool on)
 294 {
 295   uint32_t mask = (1 << (which + SR_IP_SHIFT)) & SR_IP;
 296   if (on)
 297     state.sr |= mask;
 298   else
 299     state.sr &= ~mask;
 300 }
 301
 302 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 303 {
 304   throw trap_illegal_instruction();
 305 }
 306
 307 insn_func_t processor_t::decode_insn(insn_t insn)
 308 {
 309   bool rv64 = (state.sr & SR_S) ? (state.sr & SR_S64) : (state.sr & SR_U64);
 310
 311   auto key = insn.bits() & ((1L << opcode_bits)-1);
 312   for (auto it = opcode_map.find(key); it != opcode_map.end() && it->first == key; ++it)
 313     if ((insn.bits() & it->second.mask) == it->second.match)
 314       return rv64 ? it->second.rv64 : it->second.rv32;
 315
 316   return &illegal_instruction;
 317 }
 318
 319 void processor_t::register_insn(insn_desc_t desc)
 320 {
 321   assert(desc.mask & 1);
 322   if (opcode_bits == 0 || (desc.mask & ((1L << opcode_bits)-1)) != ((1L << opcode_bits)-1))
 323   {
 324     unsigned x = 0;
 325     while ((desc.mask & ((1L << (x+1))-1)) == ((1L << (x+1))-1) &&
 326            (opcode_bits == 0 || x <= opcode_bits))
 327       x++;
 328     opcode_bits = x;
 329
 330     decltype(opcode_map) new_map;
 331     for (auto it = opcode_map.begin(); it != opcode_map.end(); ++it)
 332       new_map.insert(std::make_pair(it->second.match & ((1L<<x)-1), it->second));
 333     opcode_map = new_map;
 334   }
 335
 336   opcode_map.insert(std::make_pair(desc.match & ((1L<<opcode_bits)-1), desc));
 337 }
 338
 339 void processor_t::register_extension(extension_t* x)
 340 {
 341   for (auto insn : x->get_instructions())
 342     register_insn(insn);
 343   if (ext != NULL)
 344     throw std::logic_error("only one extension may be registered");
 345   ext = x;
 346   x->set_processor(this);
 347 }