riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  23         bool halt_on_reset)
  24   : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
  25   halt_on_reset(halt_on_reset), last_pc(1), executions(1)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31   disassembler = new disassembler_t(max_xlen);
  32
  33   reset();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdqc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = "imafdc";
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87   isa |= 1L << ('u' - 'a'); // advertise support for user mode
  88
  89   while (*p) {
  90     isa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   if (supports_extension('Q') && !supports_extension('D'))
 110     bad_isa_string(str);
 111
 112   if (supports_extension('Q') && max_xlen < 64)
 113     bad_isa_string(str);
 114
 115   max_isa = isa;
 116 }
 117
 118 void state_t::reset()
 119 {
 120   memset(this, 0, sizeof(*this));
 121   prv = PRV_M;
 122   pc = DEFAULT_RSTVEC;
 123   load_reservation = -1;
 124   tselect = 0;
 125   for (unsigned int i = 0; i < num_triggers; i++)
 126     mcontrol[i].type = 2;
 127 }
 128
 129 void processor_t::set_debug(bool value)
 130 {
 131   debug = value;
 132   if (ext)
 133     ext->set_debug(value);
 134 }
 135
 136 void processor_t::set_histogram(bool value)
 137 {
 138   histogram_enabled = value;
 139 #ifndef RISCV_ENABLE_HISTOGRAM
 140   if (value) {
 141     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 142     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 143   }
 144 #endif
 145 }
 146
 147 void processor_t::reset()
 148 {
 149   state.reset();
 150   state.dcsr.halt = halt_on_reset;
 151   halt_on_reset = false;
 152   set_csr(CSR_MSTATUS, state.mstatus);
 153
 154   if (ext)
 155     ext->reset(); // reset the extension
 156 }
 157
 158 // Count number of contiguous 0 bits starting from the LSB.
 159 static int ctz(reg_t val)
 160 {
 161   int res = 0;
 162   if (val)
 163     while ((val & 1) == 0)
 164       val >>= 1, res++;
 165   return res;
 166 }
 167
 168 void processor_t::take_interrupt(reg_t pending_interrupts)
 169 {
 170   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 171   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 172   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 173
 174   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 175   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 176   // M-ints have highest priority; consider S-ints only if no M-ints pending
 177   if (enabled_interrupts == 0)
 178     enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
 179
 180   if (state.dcsr.cause == 0 && enabled_interrupts) {
 181     // nonstandard interrupts have highest priority
 182     if (enabled_interrupts >> IRQ_M_EXT)
 183       enabled_interrupts = enabled_interrupts >> IRQ_M_EXT << IRQ_M_EXT;
 184     // external interrupts have next-highest priority
 185     else if (enabled_interrupts & (MIP_MEIP | MIP_SEIP))
 186       enabled_interrupts = enabled_interrupts & (MIP_MEIP | MIP_SEIP);
 187     // software interrupts have next-highest priority
 188     else if (enabled_interrupts & (MIP_MSIP | MIP_SSIP))
 189       enabled_interrupts = enabled_interrupts & (MIP_MSIP | MIP_SSIP);
 190     // timer interrupts have next-highest priority
 191     else if (enabled_interrupts & (MIP_MTIP | MIP_STIP))
 192       enabled_interrupts = enabled_interrupts & (MIP_MTIP | MIP_STIP);
 193     else
 194       abort();
 195
 196     throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
 197   }
 198 }
 199
 200 static int xlen_to_uxl(int xlen)
 201 {
 202   if (xlen == 32)
 203     return 1;
 204   if (xlen == 64)
 205     return 2;
 206   abort();
 207 }
 208
 209 reg_t processor_t::legalize_privilege(reg_t prv)
 210 {
 211   assert(prv <= PRV_M);
 212
 213   if (!supports_extension('U'))
 214     return PRV_M;
 215
 216   if (prv == PRV_H || !supports_extension('S'))
 217     return PRV_U;
 218
 219   return prv;
 220 }
 221
 222 void processor_t::set_privilege(reg_t prv)
 223 {
 224   mmu->flush_tlb();
 225   state.prv = legalize_privilege(prv);
 226 }
 227
 228 void processor_t::enter_debug_mode(uint8_t cause)
 229 {
 230   state.dcsr.cause = cause;
 231   state.dcsr.prv = state.prv;
 232   set_privilege(PRV_M);
 233   state.dpc = state.pc;
 234   state.pc = DEBUG_ROM_ENTRY;
 235 }
 236
 237 void processor_t::take_trap(trap_t& t, reg_t epc)
 238 {
 239   if (debug) {
 240     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 241             id, t.name(), epc);
 242     if (t.has_badaddr())
 243       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 244           t.get_badaddr());
 245   }
 246
 247   if (state.dcsr.cause) {
 248     if (t.cause() == CAUSE_BREAKPOINT) {
 249       state.pc = DEBUG_ROM_ENTRY;
 250     } else {
 251       state.pc = DEBUG_ROM_TVEC;
 252     }
 253     return;
 254   }
 255
 256   if (t.cause() == CAUSE_BREAKPOINT && (
 257               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 258               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 259               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 260     enter_debug_mode(DCSR_CAUSE_SWBP);
 261     return;
 262   }
 263
 264   // by default, trap to M-mode, unless delegated to S-mode
 265   reg_t bit = t.cause();
 266   reg_t deleg = state.medeleg;
 267   bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0;
 268   if (interrupt)
 269     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 270   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 271     // handle the trap in S-mode
 272     state.pc = state.stvec;
 273     state.scause = t.cause();
 274     state.sepc = epc;
 275     if (t.has_badaddr())
 276       state.sbadaddr = t.get_badaddr();
 277
 278     reg_t s = state.mstatus;
 279     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
 280     s = set_field(s, MSTATUS_SPP, state.prv);
 281     s = set_field(s, MSTATUS_SIE, 0);
 282     set_csr(CSR_MSTATUS, s);
 283     set_privilege(PRV_S);
 284   } else {
 285     reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0;
 286     state.pc = (state.mtvec & ~(reg_t)1) + vector;
 287     state.mepc = epc;
 288     state.mcause = t.cause();
 289     if (t.has_badaddr())
 290       state.mbadaddr = t.get_badaddr();
 291
 292     reg_t s = state.mstatus;
 293     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
 294     s = set_field(s, MSTATUS_MPP, state.prv);
 295     s = set_field(s, MSTATUS_MIE, 0);
 296     set_csr(CSR_MSTATUS, s);
 297     set_privilege(PRV_M);
 298   }
 299
 300   yield_load_reservation();
 301 }
 302
 303 void processor_t::disasm(insn_t insn)
 304 {
 305   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 306   if (last_pc != state.pc || last_bits != bits) {
 307     if (executions != 1) {
 308       fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions);
 309     }
 310
 311     fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 312             id, state.pc, bits, disassembler->disassemble(insn).c_str());
 313     last_pc = state.pc;
 314     last_bits = bits;
 315     executions = 1;
 316   } else {
 317     executions++;
 318   }
 319 }
 320
 321 int processor_t::paddr_bits()
 322 {
 323   assert(xlen == max_xlen);
 324   return max_xlen == 64 ? 50 : 34;
 325 }
 326
 327 void processor_t::set_csr(int which, reg_t val)
 328 {
 329   val = zext_xlen(val);
 330   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 331   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 332   switch (which)
 333   {
 334     case CSR_FFLAGS:
 335       dirty_fp_state;
 336       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 337       break;
 338     case CSR_FRM:
 339       dirty_fp_state;
 340       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 341       break;
 342     case CSR_FCSR:
 343       dirty_fp_state;
 344       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 345       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 346       break;
 347     case CSR_MSTATUS: {
 348       if ((val ^ state.mstatus) &
 349           (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR))
 350         mmu->flush_tlb();
 351
 352       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 353                  | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
 354                  | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
 355                  | MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL |
 356                  (ext ? MSTATUS_XS : 0);
 357
 358       reg_t requested_mpp = legalize_privilege(get_field(val, MSTATUS_MPP));
 359       state.mstatus = set_field(state.mstatus, MSTATUS_MPP, requested_mpp);
 360       if (supports_extension('S'))
 361         mask |= MSTATUS_SPP;
 362
 363       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 364
 365       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 366       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 367       if (max_xlen == 32)
 368         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 369       else
 370         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 371
 372       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 373       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 374       state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen));
 375       // U-XLEN == S-XLEN == M-XLEN
 376       xlen = max_xlen;
 377       break;
 378     }
 379     case CSR_MIP: {
 380       reg_t mask = MIP_SSIP | MIP_STIP;
 381       state.mip = (state.mip & ~mask) | (val & mask);
 382       break;
 383     }
 384     case CSR_MIE:
 385       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 386       break;
 387     case CSR_MIDELEG:
 388       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 389       break;
 390     case CSR_MEDELEG: {
 391       reg_t mask =
 392         (1 << CAUSE_MISALIGNED_FETCH) |
 393         (1 << CAUSE_BREAKPOINT) |
 394         (1 << CAUSE_USER_ECALL) |
 395         (1 << CAUSE_FETCH_PAGE_FAULT) |
 396         (1 << CAUSE_LOAD_PAGE_FAULT) |
 397         (1 << CAUSE_STORE_PAGE_FAULT);
 398       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 399       break;
 400     }
 401     case CSR_MINSTRET:
 402     case CSR_MCYCLE:
 403       if (xlen == 32)
 404         state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
 405       else
 406         state.minstret = val;
 407       break;
 408     case CSR_MINSTRETH:
 409     case CSR_MCYCLEH:
 410       state.minstret = (val << 32) | (state.minstret << 32 >> 32);
 411       break;
 412     case CSR_SCOUNTEREN:
 413       state.scounteren = val;
 414       break;
 415     case CSR_MCOUNTEREN:
 416       state.mcounteren = val;
 417       break;
 418     case CSR_SSTATUS: {
 419       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 420                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR;
 421       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 422     }
 423     case CSR_SIP: {
 424       reg_t mask = MIP_SSIP & state.mideleg;
 425       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
 426     }
 427     case CSR_SIE:
 428       return set_csr(CSR_MIE,
 429                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 430     case CSR_SPTBR: {
 431       mmu->flush_tlb();
 432       if (max_xlen == 32)
 433         state.sptbr = val & (SPTBR32_PPN | SPTBR32_MODE);
 434       if (max_xlen == 64 && (get_field(val, SPTBR64_MODE) == SPTBR_MODE_OFF ||
 435                              get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV39 ||
 436                              get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV48))
 437         state.sptbr = val & (SPTBR64_PPN | SPTBR64_MODE);
 438       break;
 439     }
 440     case CSR_SEPC: state.sepc = val; break;
 441     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 442     case CSR_SSCRATCH: state.sscratch = val; break;
 443     case CSR_SCAUSE: state.scause = val; break;
 444     case CSR_SBADADDR: state.sbadaddr = val; break;
 445     case CSR_MEPC: state.mepc = val; break;
 446     case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break;
 447     case CSR_MSCRATCH: state.mscratch = val; break;
 448     case CSR_MCAUSE: state.mcause = val; break;
 449     case CSR_MBADADDR: state.mbadaddr = val; break;
 450     case CSR_MISA: {
 451       if (!(val & (1L << ('F' - 'A'))))
 452         val &= ~(1L << ('D' - 'A'));
 453
 454       // allow MAFDC bits in MISA to be modified
 455       reg_t mask = 0;
 456       mask |= 1L << ('M' - 'A');
 457       mask |= 1L << ('A' - 'A');
 458       mask |= 1L << ('F' - 'A');
 459       mask |= 1L << ('D' - 'A');
 460       mask |= 1L << ('C' - 'A');
 461       mask &= max_isa;
 462
 463       isa = (val & mask) | (isa & ~mask);
 464       break;
 465     }
 466     case CSR_TSELECT:
 467       if (val < state.num_triggers) {
 468         state.tselect = val;
 469       }
 470       break;
 471     case CSR_TDATA1:
 472       {
 473         mcontrol_t *mc = &state.mcontrol[state.tselect];
 474         if (mc->dmode && !state.dcsr.cause) {
 475           break;
 476         }
 477         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
 478         mc->select = get_field(val, MCONTROL_SELECT);
 479         mc->timing = get_field(val, MCONTROL_TIMING);
 480         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 481         mc->chain = get_field(val, MCONTROL_CHAIN);
 482         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 483         mc->m = get_field(val, MCONTROL_M);
 484         mc->h = get_field(val, MCONTROL_H);
 485         mc->s = get_field(val, MCONTROL_S);
 486         mc->u = get_field(val, MCONTROL_U);
 487         mc->execute = get_field(val, MCONTROL_EXECUTE);
 488         mc->store = get_field(val, MCONTROL_STORE);
 489         mc->load = get_field(val, MCONTROL_LOAD);
 490         // Assume we're here because of csrw.
 491         if (mc->execute)
 492           mc->timing = 0;
 493         trigger_updated();
 494       }
 495       break;
 496     case CSR_TDATA2:
 497       if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
 498         break;
 499       }
 500       if (state.tselect < state.num_triggers) {
 501         state.tdata2[state.tselect] = val;
 502       }
 503       break;
 504     case CSR_DCSR:
 505       state.dcsr.prv = get_field(val, DCSR_PRV);
 506       state.dcsr.step = get_field(val, DCSR_STEP);
 507       // TODO: ndreset and fullreset
 508       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 509       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 510       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 511       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 512       state.dcsr.halt = get_field(val, DCSR_HALT);
 513       break;
 514     case CSR_DPC:
 515       state.dpc = val;
 516       break;
 517     case CSR_DSCRATCH:
 518       state.dscratch = val;
 519       break;
 520   }
 521 }
 522
 523 reg_t processor_t::get_csr(int which)
 524 {
 525   uint32_t ctr_en = -1;
 526   if (state.prv < PRV_M)
 527     ctr_en &= state.mcounteren;
 528   if (state.prv < PRV_S)
 529     ctr_en &= state.scounteren;
 530   bool ctr_ok = (ctr_en >> (which & 31)) & 1;
 531
 532   if (ctr_ok) {
 533     if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
 534       return 0;
 535     if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
 536       return 0;
 537   }
 538   if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 539     return 0;
 540   if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H)
 541     return 0;
 542   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
 543     return 0;
 544
 545   switch (which)
 546   {
 547     case CSR_FFLAGS:
 548       require_fp;
 549       if (!supports_extension('F'))
 550         break;
 551       return state.fflags;
 552     case CSR_FRM:
 553       require_fp;
 554       if (!supports_extension('F'))
 555         break;
 556       return state.frm;
 557     case CSR_FCSR:
 558       require_fp;
 559       if (!supports_extension('F'))
 560         break;
 561       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 562     case CSR_INSTRET:
 563     case CSR_CYCLE:
 564       if (ctr_ok)
 565         return state.minstret;
 566       break;
 567     case CSR_MINSTRET:
 568     case CSR_MCYCLE:
 569       return state.minstret;
 570     case CSR_MINSTRETH:
 571     case CSR_MCYCLEH:
 572       if (xlen == 32)
 573         return state.minstret >> 32;
 574       break;
 575     case CSR_SCOUNTEREN: return state.scounteren;
 576     case CSR_MCOUNTEREN: return state.mcounteren;
 577     case CSR_SSTATUS: {
 578       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 579                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_UXL;
 580       reg_t sstatus = state.mstatus & mask;
 581       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 582           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 583         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 584       return sstatus;
 585     }
 586     case CSR_SIP: return state.mip & state.mideleg;
 587     case CSR_SIE: return state.mie & state.mideleg;
 588     case CSR_SEPC: return state.sepc;
 589     case CSR_SBADADDR: return state.sbadaddr;
 590     case CSR_STVEC: return state.stvec;
 591     case CSR_SCAUSE:
 592       if (max_xlen > xlen)
 593         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 594       return state.scause;
 595     case CSR_SPTBR:
 596       if (get_field(state.mstatus, MSTATUS_TVM))
 597         require_privilege(PRV_M);
 598       return state.sptbr;
 599     case CSR_SSCRATCH: return state.sscratch;
 600     case CSR_MSTATUS: return state.mstatus;
 601     case CSR_MIP: return state.mip;
 602     case CSR_MIE: return state.mie;
 603     case CSR_MEPC: return state.mepc;
 604     case CSR_MSCRATCH: return state.mscratch;
 605     case CSR_MCAUSE: return state.mcause;
 606     case CSR_MBADADDR: return state.mbadaddr;
 607     case CSR_MISA: return isa;
 608     case CSR_MARCHID: return 0;
 609     case CSR_MIMPID: return 0;
 610     case CSR_MVENDORID: return 0;
 611     case CSR_MHARTID: return id;
 612     case CSR_MTVEC: return state.mtvec;
 613     case CSR_MEDELEG: return state.medeleg;
 614     case CSR_MIDELEG: return state.mideleg;
 615     case CSR_TSELECT: return state.tselect;
 616     case CSR_TDATA1:
 617       if (state.tselect < state.num_triggers) {
 618         reg_t v = 0;
 619         mcontrol_t *mc = &state.mcontrol[state.tselect];
 620         v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 621         v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 622         v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 623         v = set_field(v, MCONTROL_SELECT, mc->select);
 624         v = set_field(v, MCONTROL_TIMING, mc->timing);
 625         v = set_field(v, MCONTROL_ACTION, mc->action);
 626         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 627         v = set_field(v, MCONTROL_MATCH, mc->match);
 628         v = set_field(v, MCONTROL_M, mc->m);
 629         v = set_field(v, MCONTROL_H, mc->h);
 630         v = set_field(v, MCONTROL_S, mc->s);
 631         v = set_field(v, MCONTROL_U, mc->u);
 632         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 633         v = set_field(v, MCONTROL_STORE, mc->store);
 634         v = set_field(v, MCONTROL_LOAD, mc->load);
 635         return v;
 636       } else {
 637         return 0;
 638       }
 639       break;
 640     case CSR_TDATA2:
 641       if (state.tselect < state.num_triggers) {
 642         return state.tdata2[state.tselect];
 643       } else {
 644         return 0;
 645       }
 646       break;
 647     case CSR_TDATA3: return 0;
 648     case CSR_DCSR:
 649       {
 650         uint32_t v = 0;
 651         v = set_field(v, DCSR_XDEBUGVER, 1);
 652         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 653         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 654         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 655         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 656         v = set_field(v, DCSR_STOPCYCLE, 0);
 657         v = set_field(v, DCSR_STOPTIME, 0);
 658         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 659         v = set_field(v, DCSR_STEP, state.dcsr.step);
 660         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 661         return v;
 662       }
 663     case CSR_DPC:
 664       return state.dpc;
 665     case CSR_DSCRATCH:
 666       return state.dscratch;
 667   }
 668   throw trap_illegal_instruction(0);
 669 }
 670
 671 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 672 {
 673   throw trap_illegal_instruction(0);
 674 }
 675
 676 insn_func_t processor_t::decode_insn(insn_t insn)
 677 {
 678   // look up opcode in hash table
 679   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 680   insn_desc_t desc = opcode_cache[idx];
 681
 682   if (unlikely(insn.bits() != desc.match)) {
 683     // fall back to linear search
 684     insn_desc_t* p = &instructions[0];
 685     while ((insn.bits() & p->mask) != p->match)
 686       p++;
 687     desc = *p;
 688
 689     if (p->mask != 0 && p > &instructions[0]) {
 690       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 691         // move to front of opcode list to reduce miss penalty
 692         while (--p >= &instructions[0])
 693           *(p+1) = *p;
 694         instructions[0] = desc;
 695       }
 696     }
 697
 698     opcode_cache[idx] = desc;
 699     opcode_cache[idx].match = insn.bits();
 700   }
 701
 702   return xlen == 64 ? desc.rv64 : desc.rv32;
 703 }
 704
 705 void processor_t::register_insn(insn_desc_t desc)
 706 {
 707   instructions.push_back(desc);
 708 }
 709
 710 void processor_t::build_opcode_map()
 711 {
 712   struct cmp {
 713     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 714       if (lhs.match == rhs.match)
 715         return lhs.mask > rhs.mask;
 716       return lhs.match > rhs.match;
 717     }
 718   };
 719   std::sort(instructions.begin(), instructions.end(), cmp());
 720
 721   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 722     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 723 }
 724
 725 void processor_t::register_extension(extension_t* x)
 726 {
 727   for (auto insn : x->get_instructions())
 728     register_insn(insn);
 729   build_opcode_map();
 730   for (auto disasm_insn : x->get_disasms())
 731     disassembler->add_insn(disasm_insn);
 732   if (ext != NULL)
 733     throw std::logic_error("only one extension may be registered");
 734   ext = x;
 735   x->set_processor(this);
 736 }
 737
 738 void processor_t::register_base_instructions()
 739 {
 740   #define DECLARE_INSN(name, match, mask) \
 741     insn_bits_t name##_match = (match), name##_mask = (mask);
 742   #include "encoding.h"
 743   #undef DECLARE_INSN
 744
 745   #define DEFINE_INSN(name) \
 746     REGISTER_INSN(this, name, name##_match, name##_mask)
 747   #include "insn_list.h"
 748   #undef DEFINE_INSN
 749
 750   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 751   build_opcode_map();
 752 }
 753
 754 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 755 {
 756   switch (addr)
 757   {
 758     case 0:
 759       if (len <= 4) {
 760         memset(bytes, 0, len);
 761         bytes[0] = get_field(state.mip, MIP_MSIP);
 762         return true;
 763       }
 764       break;
 765   }
 766
 767   return false;
 768 }
 769
 770 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 771 {
 772   switch (addr)
 773   {
 774     case 0:
 775       if (len <= 4) {
 776         state.mip = set_field(state.mip, MIP_MSIP, bytes[0]);
 777         return true;
 778       }
 779       break;
 780   }
 781
 782   return false;
 783 }
 784
 785 void processor_t::trigger_updated()
 786 {
 787   mmu->flush_tlb();
 788   mmu->check_triggers_fetch = false;
 789   mmu->check_triggers_load = false;
 790   mmu->check_triggers_store = false;
 791
 792   for (unsigned i = 0; i < state.num_triggers; i++) {
 793     if (state.mcontrol[i].execute) {
 794       mmu->check_triggers_fetch = true;
 795     }
 796     if (state.mcontrol[i].load) {
 797       mmu->check_triggers_load = true;
 798     }
 799     if (state.mcontrol[i].store) {
 800       mmu->check_triggers_store = true;
 801     }
 802   }
 803 }